3.3.154 training_status

Shows information relating to the training request status of the DMC.

The training_status register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be changed.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x378
Type
Read-only
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-154 training_status register bit assignments
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The following shows the bit assignments.
[31:24] phy_training_chip
One bit per rank indicating that the PHY has an outstanding request for PHY training on the indicated DRAM rank.
[23:16] rdlvl_training_chip
One bit per rank indicating that the PHY has an outstanding request for rdlvl gate training on the indicated DRAM rank.
[15:8] rdlvl_gate_training_chip
Waiting for rdlvl gate training on the indicated DRAM rank.
[7:0] wrlvl_training_chip
One bit per rank indicating that the PHY has an outstanding request for wrlvl training on the indicated DRAM rank.
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