3.3.156 dq_map_control_15_00_next

Controls the DQ mapping compensation applied for CRC calculation. For each nibble of the DQ bus, the DIMM SPD defines a DQ Map Index to define the bit connectivity to each rank. Program the DQ Map Index retrieved from the SPD for each nibble into the corresponding register in the DMC for correct CRC operation.

The dq_map_control_15_00_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x380
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-156 dq_map_control_15_00_next register bit assignments
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The following shows the bit assignments.
[31:30] Reserved_4
Unused bits
[29:24] dq_map_15_12_next
Controls DQ mapping for bits [15:12] of the DQ bus.
[23:22] Reserved_3
Unused bits
[21:16] dq_map_11_8_next
Controls DQ mapping for bits [11:8] of the DQ bus.
[15:14] Reserved_2
Unused bits
[13:8] dq_map_7_4_next
Controls DQ mapping for bits [7:4] of the DQ bus.
[7:6] Reserved_1
Unused bits
[5:0] dq_map_3_0_next
Controls DQ mapping for bits [3:0] of the DQ bus.
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