3.3.158 dq_map_control_47_32_next

Controls the DQ mapping compensation applied for CRC calculation. For each nibble of the DQ bus, the DIMM SPD defines a DQ Map Index to define the bit connectivity to each rank. Program the DQ Map Index retrieved from the SPD for each nibble into the corresponding register in the DMC for correct CRC operation.

The dq_map_control_47_32_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x388
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-158 dq_map_control_47_32_next register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following shows the bit assignments.
[31:30] Reserved_4
Unused bits
[29:24] dq_map_47_44_next
Controls DQ mapping for bits [47:44] of the DQ bus.
[23:22] Reserved_3
Unused bits
[21:16] dq_map_43_40_next
Controls DQ mapping for bits [43:40] of the DQ bus.
[15:14] Reserved_2
Unused bits
[13:8] dq_map_39_36_next
Controls DQ mapping for bits [39:36] of the DQ bus.
[7:6] Reserved_1
Unused bits
[5:0] dq_map_35_32_next
Controls DQ mapping for bits [35:32] of the DQ bus.
Non-ConfidentialPDF file icon PDF versionARM 100000_0001_00_en
Copyright © 2014 ARM. All rights reserved.