Shows information relating to the interrupt
The dram_ecc_errc_int_info_31_00 register characteristics are:
- Usage constraints
Can be read from when in ALL states. Cannot be changed.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-175 dram_ecc_errc_int_info_31_00 register bit assignments
The following shows the bit assignments.
- [31:29] dram_ecc_errc_int_info_rank
- [28:11] dram_ecc_errc_int_info_row
- [10:1] dram_ecc_errc_int_info_column
-  dram_ecc_errc_int_info_30_00_valid
Indicates if an overflow (single interrupt overflow, or multiple interrupt overflow) has occurred and whether the interrupt information is valid. One indicates it is valid and that no overflow has occurred.