3.3.176 dram_ecc_errc_int_info_63_32

Shows information relating to the interrupt

The dram_ecc_errc_int_info_63_32 register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be changed.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x52C
Type
Read-only
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-176 dram_ecc_errc_int_info_63_32 register bit assignments
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The following shows the bit assignments.
[31] dram_ecc_errc_int_info_61_31_valid
Indicates if an overflow (single interrupt overflow, or multiple interrupt overflow) has occurred and whether the interrupt information is valid. 1 indicates it is valid and that no overflow has occurred.
[30:28] Reserved_1
Unused bits
[27:24] dram_ecc_errc_int_info_err_loc_valid
Error location valid.
[23:4] dram_ecc_errc_int_info_err_loc
Error location containing 4 sets of 5-bit nibble locations indicating which of the 18 possible nibble locations (0..17) each error was found in.
[3:0] dram_ecc_errc_int_info_bank
Bank.
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