Configures how the DRAM address is decoded from the system address. The DRAM address consists of the rank, bank, row address, and the column address.
The decode_control_now register characteristics are:
- Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG or LOW-POWER states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-190 decode_control_now register bit assignments
The following shows the bit assignments.
- [31:7] Reserved_2
- [6:4] stripe_decode_now
Determines the address boundary on which to stripe system requests across DRAM pages. The DMC
decodes the bottom two page address bits from a programmable slice
within the lowest 14 bits of the system address. To disable sub-page
striping you must program this value to the DRAM page size (or use the
default value 0).
NoteYou must not program the DMC to stripe at a higher boundary than the
DRAM page size.
- [3:2] Reserved_1
- [1:0] address_decode_now
Determines in which pattern the DRAM address components are decoded from the system address.