Configures the low-power features of the DMC.
The low_power_control_now register characteristics are:
- Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-192 low_power_control_now register bit assignments
The following shows the bit assignments.
- [31:8] Reserved_2
- [7:4] asr_period_now
Program the number of tREFI intervals to wait without activity before placing the DRAM into a self-refresh state when auto_self_refresh is enabled. The supported range for this bitfield is 1-15.
-  auto_self_refresh_now
Program to enable or disable placing a DRAM rank into a self-refresh state when the rank has been idle for the amount of time that asr_period defines.
-  auto_power_down_now
Program to enable or disable placing the DRAM into a power-down state when idle.
-  stop_mem_clock_sref_now
Program to enable or disable stopping the DRAM clock when the memory device is in self-refresh, reset, or maximum power down.
-  Reserved_1