Configures the tMRR timing parameter. This determines the Mode Register Read (including Multi-Purpose Register Reads) command delay before any other command is issued to the same rank. Use this value to determine the data cycles returned as a result of an MRR command.
The t_mrr_now register characteristics are:
- Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-274 t_mrr_now register bit assignments
The following shows the bit assignments.
- [31:9] Reserved_2
- [8:7] Reserved_1
- [6:0] t_mrr_now
The supported range for this bitfield is 1-127.