3.3.287 t_wtr_now

Configures the write-to-read timing parameter, for both same chip, other bank group (tWTR_s), same chip, same bank group (t_WTR_l), and alternate chip (tWTR_cs). These must take into account CRC timing requirements.

The t_wtr_now register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x1248
Type
Read-only
Reset
0x00040505
Width
32
The following figure shows the bit assignments.
Figure 3-287 t_wtr_now register bit assignments
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The following shows the bit assignments.
[31:22] Reserved_3
Unused bits
[21:16] t_wtr_cs_now
t_wtr_cs_now bitfield. The supported range for this bitfield is 2-63.
[15:14] Reserved_2
Unused bits
[13:8] t_wtr_l_now
t_wtr_l_now bitfield. The supported range for this bitfield is 5-63.
[7:6] Reserved_1
Unused bits
[5:0] t_wtr_s_now
t_wtr_s_now bitfield. The supported range for this bitfield is 5-63.
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