Configures the delay between entering self-refresh and disabling the DRAM clock. This parameter is applied when stopping the clock when in self-refresh and when in a maximum power-down state.
The t_esrck_now register characteristics are:
- Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-294 t_esrck_now register bit assignments
The following shows the bit assignments.
- [31:5] Reserved_1
- [4:0] t_esrck_now
The supported range for this bitfield is 1-31.