3.3.301 t_phywrlat_now

Determines the time between a WRITE command commencing on the DFI interface, and the assertion of the dfi_wrdata_en, dfi_wrdata_cs and dfi_wrdata signals.

The t_phywrlat_now register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x1308
Type
Read-only
Reset
0x00000001
Width
32
The following figure shows the bit assignments.
Figure 3-301 t_phywrlat_now register bit assignments
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The following shows the bit assignments.
[31:25] Reserved_4
Unused bits
[24] t_phywrdata_now
Determines the time between the assertion of the dfi_wrdata_en and dfi_wrdata signals. The supported range for this bitfield is 0-1.
[23:21] Reserved_3
Unused bits
[20:16] t_phywrcslat_now
Specifies the number of DFI PHY clocks between when a write command is sent on the DFI control interface (dfi_cs_n assertion) and when the associated dfi_wrdata_cs_n signal is asserted. The supported range for this bitfield is 0-31.
[15:13] Reserved_2
Unused bits
[12:8] t_phywrlat_diff_now
Describes the PHY specific value useful for aligning t_phywrlat for a specific PHY. This value has no effect on the controller. The supported range for this bitfield is 0-31.
[7:5] Reserved_1
Unused bits
[4:0] t_phywrlat_now
Determines the time between a WRITE command commencing on the DFI interface, and the assertion of the dfi_wrdata_en signal. The supported range for this bitfield is 0-31.
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