Determines the Mode Register command to use to place the DRAM into a training mode for read training, when enabled by the rdlvl_control register. See the PHY interface section of the Integration Manual for more information on PHY training.
The rdlvl_mrs_now register characteristics are:
- Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-303 rdlvl_mrs_now register bit assignments
The following shows the bit assignments.
- [31:13] Reserved_1
- [12:0] rdlvl_mrs_now
Program the Mode Register command the DMC uses to place the DRAM into training mode. Set address bits [2:0] for the Mode Register write to MR3.