Configures the t_rdlvl_rr timing parameter. This specifies the cycle delay between training commands. It also specifies the minimum delay between the last training command and deasserting dfi_rdlvl_en after observing dfi_rdlvl_resp.
The t_rdlvl_rr_now register characteristics are:
- Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-305 t_rdlvl_rr_now register bit assignments
The following shows the bit assignments.
- [31:10] Reserved_1
- [9:0] t_rdlvl_rr_now
The supported range for this bitfield is 4-1023.