3.3.308 t_wrlvl_en_now

Configures the t_wrlvl_en timing parameter. Specifies the cycle delay between asserting ODT for training and asserting dfi_wrlvl_en, the delay between asserting dfi_wrlvl_en and the first training command, the delay between deasserting dfi_wrlvl_en and de-asserting ODT, and deasserting ODT to any subsequent command. It is also used between ODT transitions and refreshes generated during training.

The t_wrlvl_en_now register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x1328
Type
Read-only
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-308 t_wrlvl_en_now register bit assignments
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The following shows the bit assignments.
[31:6] Reserved_1
Unused bits
[5:0] t_wrlvl_en_now
t_wrlvl_en_now bitfield. The supported range for this bitfield is 1-63.
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