3.3.315 odt_wr_control_63_32_now

Configures the ODT on and off settings for active and inactive ranks during writes.

The odt_wr_control_63_32_now register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x1364
Type
Read-only
Reset
0x80402010
Width
32
The following figure shows the bit assignments.
Figure 3-315 odt_wr_control_63_32_now register bit assignments
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The following shows the bit assignments.
[31:24] odt_mask_wr_cs7_now
Drives the dfi_odt[7:0] output signal during a write to DRAM rank 7. The supported range for this bitfield is 0-255.
[23:16] odt_mask_wr_cs6_now
Drives the dfi_odt[7:0] output signal during a write to DRAM rank 6. The supported range for this bitfield is 0-255.
[15:8] odt_mask_wr_cs5_now
Drives the dfi_odt[7:0] output signal during a write to DRAM rank 5. The supported range for this bitfield is 0-255.
[7:0] odt_mask_wr_cs4_now
Drives the dfi_odt[7:0] output signal during a write to DRAM rank 4. The supported range for this bitfield is 0-255.
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