3.3.321 dq_map_control_63_48_now

Controls the DQ mapping compensation applied for CRC calculation. For each nibble of the DQ bus, the DIMM SPD defines a DQ Map Index to define the bit connectivity to each rank. Program the DQ Map Index retrieved from the SPD for each nibble into the corresponding register in the DMC for correct CRC operation.

The dq_map_control_63_48_now register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x138C
Type
Read-only
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-321 dq_map_control_63_48_now register bit assignments
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The following shows the bit assignments.
[31:30] Reserved_4
Unused bits
[29:24] dq_map_63_60_now
Controls DQ mapping for bits [63:60] of the DQ bus.
[23:22] Reserved_3
Unused bits
[21:16] dq_map_59_56_now
Controls DQ mapping for bits [59:56] of the DQ bus.
[15:14] Reserved_2
Unused bits
[13:8] dq_map_55_52_now
Controls DQ mapping for bits [55:52] of the DQ bus.
[7:6] Reserved_1
Unused bits
[5:0] dq_map_51_48_now
Controls DQ mapping for bits [51:48] of the DQ bus.
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