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ARM® CoreLink™ DMC-520 Dynamic Memory Controller Technical Reference ManualRevision r0p1
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3.3.322 dq_map_control_71_64_now

Controls the DQ mapping compensation applied for CRC calculation. For each nibble of the DQ bus, the DIMM SPD defines a DQ Map Index to define the bit connectivity to each rank. Program the DQ Map Index retrieved from the SPD for DIMM Check Bits bus into this register in the DMC for correct CRC operation.

The dq_map_control_71_64_now register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x1390
Type
Read-only
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-322 dq_map_control_71_64_now register bit assignments
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The following shows the bit assignments.
[31:24] Reserved_3
Unused bits
[23:16] rank_dq_bit_swap_now
Each bit determines if the DQ bus has bit swapping as per the DDR4 RDIMM Design Specification applied to the corresponding rank. Normally, this bit must be set high for odd physical ranks.
[15:14] Reserved_2
Unused bits
[13:8] dq_map_71_68_now
Controls DQ mapping for bits [71:68] of the DQ bus. This corresponds to CB [7:4] on the DIMM.
[7:6] Reserved_1
Unused bits
[5:0] dq_map_67_64_now
Controls DQ mapping for bits [67:64] of the DQ bus. This corresponds to CB [3:0] on the DIMM.
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