3.3.4 Imprecise Error Register

This register records the CCI-500 interfaces that have encountered an error that cannot be signaled precisely.

A register bit corresponding to a CCI-500 interface is set when one or more error responses are detected on that interface. Each bit is reset on a write of 1 to that bit.
Usage constraints
Accessible using only Secure accesses, unless you set the Secure Access Register. See 3.3.2 Secure Access Register.
Configurations
Available in all CCI-500 configurations.
Attributes
See Table 1.

Note

If any bits are set in this register, the nERRIRQ signal is asserted, active LOW.
The following figure shows the bit assignments.
Figure 3-4 impr_err register bit assignments
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The following table shows the bit assignments.

Table 3-5 impr_err register bit assignments

Bits
Name
Function
[31:23]
Reserved_2
-
[22]
imprecise_error_indicator_si6
Imprecise error indicator for slave interface 6:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[21]
imprecise_error_indicator_si5
Imprecise error indicator for slave interface 5:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[20]
imprecise_error_indicator_si4
Imprecise error indicator for slave interface 4:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[19]
imprecise_error_indicator_si3
Imprecise error indicator for slave interface 3:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[18]
imprecise_error_indicator_si2
Imprecise error indicator for slave interface 2:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[17]
imprecise_error_indicator_si1
Imprecise error indicator for slave interface 1:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[16]
imprecise_error_indicator_si0
Imprecise error indicator for slave interface 0:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[15:6]
Reserved_1
-
[5]
imprecise_error_indicator_mi5
Imprecise error indicator for master interface 5:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[4]
imprecise_error_indicator_mi4
Imprecise error indicator for master interface 4:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[3]
imprecise_error_indicator_mi3
Imprecise error indicator for master interface 3:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[2]
imprecise_error_indicator_mi2
Imprecise error indicator for master interface 2:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[1]
imprecise_error_indicator_mi1
Imprecise error indicator for master interface 1:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
[0]
imprecise_error_indicator_mi0
Imprecise error indicator for master interface 0:
0No error from the time this bit was last reset.
1An error response has been received, but not signaled precisely.
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