1.1 About the CoreLink CCI-500
Cache Coherent Interconnect
The CCI-500 is a programmable high bandwidth interconnect that enables hardware-coherent systems.
Hardware-managed coherency can improve system performance and reduce system
power by sharing on-chip data. Managing coherency in hardware has the following benefits:
- Reduces external memory accesses.
- Reduces the software
- Enables use of ARM®
big.LITTLE™ processing with multiple processor
is a configurable interconnect that supports connectivity of:
- Up to four AMBA 4 ACE masters, such as the ARM
Cortex®-A57 or Cortex-A53 processors.
- Up to six AMBA 4 ACE-Lite masters, such as the ARM
- Up to six AMBA 4 AXI4 slaves, such as memory and system peripherals.
permits combinations of ACE and ACE-Lite masters, up to a maximum total of seven
The CCI-500 AXI4
master interfaces provide connection to memory and peripheral address space.