The CCI-500 is
highly-configurable. You can select how many master and slave components to include in your
system. The following figure shows an example CCI-500-based system.
Figure 1-1 Example system with a CCI-500
In this example, slave interfaces S5 to S6 support the ACE protocol for
connecting masters such as the Cortex-A53 or Cortex-A57 processors. The CCI-500 manages full coherency and data
sharing between L1 and L2 caches of all connected processor clusters. Optionally, you can use
the ADB-400 asynchronous bridge between components to integrate multiple power domains or
Slave interfaces S0 to S4 support ACE-Lite and DVM signaling for connecting
I/O coherent devices such as the Mali-T760 graphics unit. You can use DVM signaling for MMUs
such as the MMU-500.
You can use the
interface to program the CCI-500
Typically, up to four AXI4 master interfaces are connected to compatible
memory controllers for LPDDR4 and LPDDR3 memory. Interfaces M5-M2 in the figure show these
Typically, up to two AXI4 master interfaces are connected to system
components, as shown by interfaces M1 and M0.
clock and power control is achieved using the Q-Channel and the