A.5 DFT signals

The CCI-500 uses the Design For Test (DFT) signals to communicate with the DFT and MBIST interfaces.

The following table shows the DFT signals.

Table A-5 DFT signals

Signal
Direction
Description
DFTRSTDISABLE
Input
Disables reset during scan shift.
DFTCGEN
Input
Assert HIGH during scan shift to enable architectural clock gates for ACLK clocks.
DFTRAMHOLD
Input
Blocks chip select to RAMs to preserve state.
DFTMCPHOLD
Input
Limits number of multi-cycle path toggles during ATPG delay test.
nMBISTRESET0
Input
Resets MBIST mode.
MBISTREQ0
Input
Selects MBIST mode.
MBISTACK0
Output
Acknowledges MBIST mode.
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