A.7.4 Read address channel signals

The following table shows the read address channel signals.

Table A-10 Read address channel signals

Signal
Direction
Description
ARIDSx[n:0]
Input
Read address ID. You can configure the width of this signal.
ARADDRSx[n:0]
Input
Read address. You can configure the CCI-500 to support 40-bit [39:0], or 44-bit [43:0] DVM transactions.
ARREGIONSx[3:0]
Input
Read address region. You can tie this signal LOW if the master does not drive it.
ARLENSx[7:0]
Input
Read burst length.
ARSIZESx[2:0]
Input
Read burst size.
ARBURSTSx[1:0]
Input
Read burst type.
ARLOCKSx
Input
Read lock type.
ARCACHESx[3:0]
Input
Read cache type.
ARPROTSx[2:0]
Input
Read protection type.
ARDOMAINSx[1:0]
Input
Read domain.
ARSNOOPSx[3:0]
Input
Read snoop request type.
ARQOSSx[3:0]
Input
Read QoS.
ARUSERSx[n:0]
Input
The specified extension to the AR payload.
NSAIDRSx[3:0]
Input Optional extension to AR payload, that transmits the Non-secure access identifier for a request.
ARVALIDSx
Input
Read address is valid.
ARREADYSx
Output
Read address is ready.
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