2.4.7 Error responses

The CCI-500 uses a combination of precise and imprecise error responses. Precise errors are signaled on the response to the request that caused the error. With the exception of DVM or Evict requests, for accesses to regions that are not mapped in the address decoder, the CCI-500 generates a DECERR response and any snoops, or snoop filter updates, are suppressed. The address map is implementation specific. See your platform documentation for more information.

A snoop error response to a CleanInvalid, CleanShared, or MakeInvalid transaction generates a SLVERR response to the originating device.
There are certain circumstances when it is not possible to signal an error precisely. In these cases, the CCI-500 signals an error imprecisely, using the nERRIRQ output pin. You can identify the interface that received the error response by reading the 3.3.4 Imprecise Error Register.
The following table shows the errors that are signaled as imprecise. All other sources of error are signaled precisely.

Note

An error is signaled either precisely or imprecisely, but never both.

Table 2-6 Imprecise errors

Error condition
Channel receiving error
Imprecise error indicator from
A snoop hit response with the error bit set, where data from another snooped master is returned instead of this one.
CR
Slave interface receiving the CR response.
A snoop miss response with the error bit set.
CR
Slave interface receiving the CR response.
Write access generated by the CCI-500.
B
Master interface receiving the B response.
A snoop response with the error bit set where the snoop was generated from a WriteLineUnique or WriteUnique transaction.
CR
Master interface receiving the CR response.
A snoop response with the error bit set where the snoop was generated from a back-invalidation.
CR
Slave interface receiving the CR response.
The CCI-500 generates a precise error response for a security violation on a CCI-500 register access. See 2.4.6 Security.
Non-ConfidentialPDF file icon PDF versionARM 100023_0001_00_en
Copyright © 2014, 2015 ARM. All rights reserved.