B.1 Revisions

This appendix describes the technical changes between released issues of this book.

Table B-1 Issue 0000-00

Change
Location
Affects
First release
-
-

Table B-2 Differences between Issue 0000-00 and Issue 0000-01

Change
Location
Affects
Clarified information about adding and removing masters from the coherent domain.
All revisions.
Updated information about relationship between debug enable inputs and PMCR settings.
All revisions.

Table B-3 Differences between Issue 0000-01 and Issue 0001-00

Change
Location
Affects
Clarified description of snoop filter directory configuration.
All revisions.
Clarified procedure for removing a master from the coherent domain.
All revisions.
Clarified the example of how to use the PMU.
All revisions.
Amended register names to match RTL names.
All revisions.
Revised peripheral_id2 entry.
r0p1.
Amended some register bit names and field names for consistency with other ARM documents.
All revisions.
Clarified configurations descriptions to indicate that certain registers have multiple copies.
All revisions.
Amended usage constraints.
Amended access permissions of bits[15:11].
r0p1.
Amended usage constraints.
r0p1.
Revised peripheral_id2.
r0p1.
Clarified bit assignment descriptions.
All revisions.
Clarified bit assignment descriptions for bits[7:0].
All revisions.
Clarified bit assignment descriptions for bits[4:0].
All revisions.
Amended example address map.
All revisions.
Added note to clarify description of 0b111 setting for ADDRMAP[2:0].
All revisions.
Clarified ORDERED_WRITE_OBSERVATION[n:0] description.
r0p1.
Added NSAID_ENABLED_Sx signal.
All revisions.
Added MI_DEPENDENT_ON_SI_Mx signal.
r0p1.
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