ARM® CoreLink™ CCI-500 Cache Coherent Interconnect Technical Reference Manual

Revision r0p2


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the CCI-500
1.2 Compliance
1.3 Features
1.4 Interfaces
1.5 CCI operation
1.6 Configurable options
1.7 Test features
1.8 Product design flow and documentation
1.8.1 Documentation
1.9 Product revisions
2 Functional Description
2.1 About the functions
2.2 Interfaces
2.2.1 ACE interfaces
2.2.2 ACE-Lite slave interfaces
2.2.3 AXI4 master interfaces
2.2.4 APB4 slave interface
2.2.5 Clock and power control interfaces
2.2.6 Debug and performance monitoring interface
2.2.7 DFT interface
2.3 Clocking and reset
2.4 Operation
2.4.1 Connectivity and address map
2.4.2 Snoop filter
2.4.3 Snoop connectivity and control
2.4.4 Performance Monitoring Unit
2.4.5 Debug features
2.4.6 Security
2.4.7 Error responses
2.4.8 Cache maintenance operations
2.4.9 Barriers
2.4.10 Exclusive accesses
2.4.11 DVM messages
2.4.12 Quality of Service
3 Programmers Model
3.1 About this programmers model
3.2 Register summary
3.3 Register descriptions
3.3.1 Control Override Register
3.3.2 Secure Access Register
3.3.3 Status Register
3.3.4 Imprecise Error Register
3.3.5 QoS Threshold Register
3.3.6 Performance Monitor Control Register (PMCR)
3.3.7 Interface Monitor Control Register
3.3.8 Component and Peripheral ID Registers
3.3.9 Snoop Control Registers
3.3.10 Shareable Override Register
3.3.11 Read Channel QoS Value Override Register
3.3.12 Write Channel QoS Value Override Register
3.3.13 Maximum Outstanding Transactions Registers
3.3.14 Event Select Registers
3.3.15 Event Count Registers
3.3.16 Count Control Registers
3.3.17 Overflow Flag Status Registers
3.3.18 Slave Interface Monitor Registers
3.3.19 Master Interface Monitor Registers
3.4 Address map
A Signal Descriptions
A.1 Clock and reset signals
A.2 Power and clock control signals
A.3 Configuration signals
A.4 Debug signals
A.5 DFT signals
A.6 APB4 signals
A.7 ACE and ACE-Lite slave interface signals
A.7.1 Write address channel signals
A.7.2 Write data channel signals
A.7.3 Write data response channel signals
A.7.4 Read address channel signals
A.7.5 Read data channel signals
A.7.6 Coherency address channel signals
A.7.7 Coherency response channel signals
A.7.8 Coherency data channel signals for ACE interfaces
A.7.9 Acknowledge signals for ACE interfaces
A.8 AXI master interface signals
A.8.1 Write address channel signals
A.8.2 Write data channel signals
A.8.3 Write data response channel signals
A.8.4 Read address channel signals
A.8.5 Read data channel signals
A.9 Miscellaneous signals
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 27 November 2014 Non-Confidential First release for r0p0.
0000-01 19 December 2014 Confidential Second release for r0p0.
0001-00 19 March 2015 Non-Confidential First release for r0p1.
0000-02 06 May 2015 Non-Confidential Non-technical update for r0p0.
0002-00 17 September 2015 Non-Confidential First release for r0p2.

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