Arm® Cortex®-R52 Processor Technical Reference Manual

Revision r1p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the Cortex®-R52 processor
1.1.1 Features
1.1.2 Interfaces
1.1.3 Configuration options
1.2 Component blocks
1.2.1 Instruction Fetch
1.2.2 Advanced SIMD and floating-point support
1.2.3 GIC Distributor
1.2.4 GIC CPU interface
1.2.5 Memory system
1.2.6 Memory management
1.2.7 Debug, trace, and test
1.3 Interfaces
1.3.1 Advanced Microcontroller Bus Architecture (AMBA) interfaces
1.3.2 Flash interface
1.3.3 Memory Reconstruction Port
1.3.4 Interrupt interface
1.3.5 MBIST interface
1.3.6 Low Power Interface
1.4 Supported standards
1.4.1 Arm architecture
1.4.2 AMBA
1.4.3 Generic Interrupt Controller architecture
1.4.4 Generic Timer architecture
1.4.5 Debug architecture
1.4.6 Embedded Trace Macrocell architecture
1.5 Documentation
1.6 Design process
1.7 Product revisions
2 Programmers Model
2.1 About the programmers model
2.1.1 Advanced SIMD and Floating-point
2.1.2 Generic Interrupt Controller
2.1.3 Jazelle implementation
2.1.4 Instruction set states
2.1.5 Memory model
2.1.6 Security state
2.2 Armv8-R architecture concepts
2.2.1 Execution state
2.2.2 Exception levels
2.2.3 Typical exception level usage model
2.2.4 Exception terminology
2.2.5 Instruction set state
2.2.6 AArch32 execution modes
2.2.7 Support for v8 memory types
2.2.8 System registers
2.2.9 General purpose registers
2.2.10 Program status registers
2.2.11 Data types
2.2.12 Memory model
2.2.13 GIC Architecture
3 System Control
3.1 About system control
3.2 Register summary
3.2.1 c0 registers
3.2.2 c1 registers
3.2.3 c2 registers
3.2.4 c3 registers
3.2.5 c4 registers
3.2.6 c5 registers
3.2.7 c6 registers
3.2.8 c7 registers
3.2.9 c7 System operations
3.2.10 c8 System operations
3.2.11 c9 registers
3.2.12 c10 registers
3.2.13 c11 registers
3.2.14 c12 registers
3.2.15 c13 registers
3.2.16 c14 registers
3.2.17 c15 registers
3.2.18 64-bit registers
3.2.19 AArch32 Identification registers
3.2.20 AArch32 Memory control registers
3.2.21 AArch32 Exception and fault handling registers
3.2.22 AArch32 Other system control registers
3.2.23 AArch32 Address registers
3.2.24 AArch32 Thread registers
3.2.25 AArch32 Performance monitor registers
3.2.26 AArch32 Virtualization registers
3.2.27 AArch32 GIC system registers
3.2.28 AArch32 Generic Timer registers
3.2.29 AArch32 Implementation defined registers
3.2.30 AArch32 Implementation defined operations
3.2.31 AArch32 Debug registers
3.2.32 AArch32 Reset management registers
3.2.33 AArch32 Legacy feature registers
3.2.34 AArch32 Cache maintenance instructions
3.2.35 AArch32 Security registers
3.2.36 AArch 32 PMSA-specific registers
3.3 AArch32 register descriptions
3.3.1 Architectural Feature Access Control Register
3.3.2 Auxiliary Control Register
3.3.3 Auxiliary Control Register 2
3.3.4 Auxiliary Data Fault Status Register
3.3.5 Auxiliary Feature Register 0
3.3.6 Auxiliary ID Register
3.3.7 Auxiliary Instruction Fault Status Register
3.3.8 Auxiliary Memory Attribute Indirection Register 0
3.3.9 Auxiliary Memory Attribute Indirection Register 1
3.3.10 Branch Predictor Control Register
3.3.11 Build Options Register
3.3.12 Bus Timeout Register
3.3.13 Cache Level ID Register
3.3.14 Cache Segregation Control Register
3.3.15 Cache Size Selection Register
3.3.16 Cache Type Register
3.3.17 Configuration Base Address Register
3.3.18 Context ID Register
3.3.19 CPU Auxiliary Control Register
3.3.20 Current Cache Size ID Register
3.3.21 Data Cache Error Record Registers 0 and 1
3.3.22 Data Fault Address Register
3.3.23 Data Fault Status Register
3.3.24 Debug Feature Register 0
3.3.25 EL0 Read/Write Software Thread ID Register
3.3.26 EL0 Read-Only Software Thread ID Register
3.3.27 EL1 Software Thread ID Register
3.3.28 FCSE Process ID Register
3.3.29 Flash Error Record Registers 0 and 1
3.3.30 Flash Interface Region Register
3.3.31 Hyp Architectural Feature Trap Register
3.3.32 Hyp Auxiliary Configuration Register
3.3.33 Hyp Auxiliary Control Register
3.3.34 Hyp Auxiliary Control Register 2
3.3.35 Hyp Auxiliary Data Fault Status Register
3.3.36 Hyp Auxiliary Instruction Fault Status Register
3.3.37 Hyp Auxiliary Memory Attribute Indirection Register 0
3.3.38 Hyp Auxiliary Memory Attribute Indirection Register 1
3.3.39 Hyp Configuration Register
3.3.40 Hyp Configuration Register 2
3.3.41 Hyp Data Fault Address Register
3.3.42 Hyp Debug Control Register
3.3.43 Hyp Instruction Fault Address Register
3.3.44 Hyp IPA Fault Address Register
3.3.45 Hyp Memory Attribute Indirection Register 0 and 1
3.3.46 Hyp MPU Region Enable Register
3.3.47 Hyp MPU Type Register
3.3.48 Hyp Protection Region Base Address Register
3.3.49 Hyp Protection Region Limit Address Register
3.3.50 Hyp Protection Region Selection Register
3.3.51 Hyp Software Thread ID Register
3.3.52 Hyp Syndrome Register
3.3.53 Hyp System Control Register
3.3.54 Hyp System Trap Register
3.3.55 Hyp Vector Base Address Register
3.3.56 Hypervisor Reset Management Register
3.3.57 Instruction Cache Error Record Registers 0 and 1
3.3.58 Instruction Fault Address Register
3.3.59 Instruction Fault Status Register
3.3.60 Instruction Set Attribute Register 0
3.3.61 Instruction Set Attribute Register 1
3.3.62 Instruction Set Attribute Register 2
3.3.63 Instruction Set Attribute Register 3
3.3.64 Instruction Set Attribute Register 4
3.3.65 Instruction Set Attribute Register 5
3.3.66 Interrupt Monitoring Register
3.3.67 Interrupt Status Register
3.3.68 Invalidate All Register
3.3.69 Main ID Register
3.3.70 Memory Attribute Indirection Registers 0 and 1
3.3.71 Memory Model Feature Register 0
3.3.72 Memory Model Feature Register 1
3.3.73 Memory Model Feature Register 2
3.3.74 Memory Model Feature Register 3
3.3.75 Memory Model Feature Register 4
3.3.76 Memory Protection Control Register
3.3.77 MPU Type Register
3.3.78 Multiprocessor Affinity Register
3.3.79 Non-Secure Access Control Register
3.3.80 Peripheral Port Region Register
3.3.81 Physical Address Register
3.3.82 Pin Options Register
3.3.83 Processor Feature Register 0
3.3.84 Processor Feature Register 1
3.3.85 Protection Region Base Address Register
3.3.86 Protection Region Limit Address Register
3.3.87 Protection Region Selection Register
3.3.88 Quality Of Service Register
3.3.89 Reset Vector Base Address Register
3.3.90 Revision ID Register
3.3.91 Slave Port Control Register
3.3.92 System Control Register
3.3.93 TCM Error Record Register 0 and 1
3.3.94 TCM Region Registers A, B, and C
3.3.95 TCM Syndrome Register 0 and 1
3.3.96 TCM Type Register
3.3.97 Test Register 0
3.3.98 TLB Type Register
3.3.99 Vector Base Address Register
3.3.100 Virtualization Multiprocessor ID Register
3.3.101 Virtualization Processor ID Register
3.3.102 Virtualization System Control Register
4 Clocking and Resets
4.1 Clock and clock enables
4.2 Reset signals
4.3 Reset-related signals
5 Power Management
5.1 About power management
5.2 Local and regional clock gating
5.3 Architectural clock gating
5.3.1 WFI low-power state
5.3.2 WFE low-power state
5.3.3 Event communication using WFE and SEV instructions
5.3.4 CLREXMON request and acknowledge signaling
5.4 Power gating
5.4.1 Power domains
5.4.2 Cortex-R52 LPI
5.4.3 Powerdown sequence
5.4.4 Powerup sequence
5.4.5 Debug over powerdown
5.4.6 Powerdown of the cluster
6 Initialization
6.1 Initialization
6.1.1 MPU
6.1.2 Floating-point Unit
6.1.3 Caches
6.2 TCM
6.2.1 Preloading TCMs
6.2.2 Preloading TCMs with ECC
6.2.3 Using TCMs from reset
6.3 Entering EL1
7 Memory System
7.1 About the memory system
7.2 TCM memory
7.3 Level-1 caches
7.3.1 Cache segregation
7.3.2 Data cache invalidation
7.3.3 Write streaming mode
7.4 Direct access to internal memory
7.4.1 Data cache tag and data encoding
7.4.2 Instruction cache tag and data encoding
7.5 AXIM interface
7.5.1 AXIM interface attributes
7.5.2 AXIM interface transfers
7.5.3 AXIM data prefetchers
7.5.4 AXIM transaction IDs
7.5.5 AXI privilege information
7.5.6 AXIM QoS and user signals
7.5.7 AXIM interface timeout
7.6 Low-latency peripheral port
7.6.1 LLPP Memory attributes
7.6.2 LLPP AXI transfer restrictions
7.6.3 LLPP timeout
7.7 Flash interface
7.7.1 Flash interface timeout
7.8 AXIS interface
7.8.1 Accessing TCM with ECC
7.8.2 AXIS characteristics
7.9 Error detection and handling
7.9.1 TCM error detection and correction
7.9.2 Cache memory ECC
7.9.3 ECC error reporting
7.9.4 Bus protection
7.9.5 Flash data ECC
7.10 Exclusive accesses
7.11 Bus timeouts
8 Memory Protection Unit
8.1 About the MPU
8.2 MPU regions
8.2.1 EL1-controlled MPU background region
8.2.2 EL2-controlled MPU background region
8.2.3 Default cacheability
8.3 Virtualization support
8.3.1 Combining MPU memory attributes
8.4 MPU register access
8.5 MPU Register summary
9 Generic Interrupt Controller
9.1 About the GIC
9.2 GIC functional description
9.2.1 GIC Distributor memory map
9.2.2 Interrupt sources
9.2.3 Optional export interface
9.3 GIC programmers model
9.3.1 Distributor Registers (GICD)
9.3.2 Redistributor Registers (GICR)
9.3.3 Hypervisor Control System Registers
9.3.4 CPU Interface Registers
9.3.5 Virtual CPU Interface Registers
10 Generic Timer
10.1 About the Generic Timer
10.2 Generic Timer functional description
10.3 Generic Timer register summary
10.3.1 AArch32 Generic Timer register summary
11 Debug
11.1 About Debug
11.1.1 External debug
11.1.2 Self-hosted debug
11.1.3 The debug model
11.2 Debug register interfaces
11.2.1 Processor interfaces
11.2.2 Breakpoints and watchpoints
11.2.3 Effects of resets on debug registers
11.2.4 External register access permissions
11.3 System register summary
11.4 System register descriptions
11.4.1 Debug ID Register
11.4.2 Debug Device ID Register
11.4.3 Debug Device ID Register 1
11.5 Memory-mapped register summary
11.6 Memory-mapped register descriptions
11.6.1 External Debug Calibration Control Register
11.6.2 External Debug Reserve Control Register
11.6.3 External Debug Device ID Register 0
11.6.4 External Debug Device ID Register 1
11.6.5 External Debug Peripheral Identification Registers
11.6.6 External Debug Component Identification Registers
11.6.7 External Debug AArch32 Processor Feature Register
11.6.8 External Debug Processor Feature Register
11.6.9 External Debug Feature Register
11.7 External debug interface
11.7.1 Debug memory map
11.7.2 Debug power interface
11.7.3 Debug over warm reset
11.7.4 Changing the authentication signals
11.8 ROM table
11.8.1 ROM table register summary
11.8.2 ROM table register descriptions
11.8.3 ROM table Debug Peripheral Identification Registers
11.8.4 ROM table Debug Component Identification Registers
12 Performance Monitor Unit
12.1 About the PMU
12.1.1 Event interface
12.1.2 System register and APB interface
12.1.3 Counters
12.1.4 External register access permissions
12.1.5 Authentication signals and PMU behavior
12.2 PMU register summary
12.3 PMU register descriptions
12.3.1 Performance Monitors Control Register
12.3.2 Performance Monitors Common Event Identification Register 0
12.3.3 Performance Monitors Common Event Identification Register 1
12.4 Memory-mapped register summary
12.5 Memory-mapped register descriptions
12.5.1 Performance Monitor Configuration Register
12.5.2 Performance Monitors Peripheral Identification Registers
12.5.3 Performance Monitors Component Identification Registers
12.6 Events
12.7 Interrupts
12.8 Exporting PMU events
12.8.1 External hardware
12.8.2 Debug trace hardware
13 Cross Trigger
13.1 About the cross trigger
13.2 Trigger inputs and outputs
13.3 Cortex®-R52 CTM
13.4 Cross trigger register summary
13.4.1 External register access permissions
13.5 Cross trigger register descriptions
13.5.1 CTI Device Identification Register
13.5.2 CTI Integration Mode Control Register
13.5.3 CTI Peripheral Identification Registers
13.5.4 Component Identification Registers
14 Embedded Trace Macrocell
14.1 About the ETM
14.1.1 Processor interface
14.1.2 Instruction trace generator
14.1.3 Data trace generator
14.1.4 FIFO
14.1.5 Resources and filtering logic
14.1.6 ATB interfaces
14.1.7 APB interface
14.1.8 Global timestamping
14.2 ETM trace unit generation options and resources
14.3 ETM Event connectivity
14.4 Operation
14.4.1 Implementation defined registers
14.4.2 Precise TraceEnable events
14.4.3 Parallel instruction execution
14.4.4 Comparator features
14.4.5 Trace features
14.4.6 Packet formats
14.4.7 Resource selection
14.4.8 Trace flush behavior
14.4.9 Low power state behavior
14.4.10 Cycle counter
14.4.11 Non-architectural exceptions
14.4.12 Trace synchronization
14.5 Modes of operation and execution
14.5.1 Use of the ETM main enable bit
14.5.2 Programming and reading ETM registers
14.5.3 External register access permissions
14.6 Register summary
14.7 Register descriptions
14.7.1 Programming Control Register
14.7.2 Status Register
14.7.3 Trace Configuration Register
14.7.4 Event Control 0 Register
14.7.5 Event Control 1 Register
14.7.6 Stall Control Register
14.7.7 Global Timestamp Control Register
14.7.8 Synchronization Period Register
14.7.9 Cycle Count Control Register
14.7.10 Branch Broadcast Control Register
14.7.11 Trace ID Register
14.7.12 ViewInst Main Control Register
14.7.13 ViewInst Include/Exclude Control Register
14.7.14 ViewInst Start/Stop Control Register
14.7.15 ViewData Main Control Register
14.7.16 ViewData Include/Exclude Single Address Comparator Register
14.7.17 ViewData Include/Exclude Address Range Comparator Register
14.7.18 Sequencer State Transition Control Registers, n=0-2
14.7.19 Sequencer Reset Control Register
14.7.20 Sequencer State Register
14.7.21 External Input Select Register
14.7.22 Counter Reload Value Registers, n=0-1
14.7.23 Counter Control Registers 0-1
14.7.24 Counter Value Registers, n=0-1
14.7.25 ID Registers, n=8-13
14.7.26 Implementation Specific Register 0
14.7.27 ID Register 0
14.7.28 ID Register 1
14.7.29 ID Register 2
14.7.30 ID Register 3
14.7.31 ID Register 4
14.7.32 ID Register 5
14.7.33 Resource Selection Registers, n=2-15
14.7.34 Single-shot Comparator Control Registers, n=0-1
14.7.35 Single-shot Comparator Status Registers n=0-1
14.7.36 OS Lock Access Register
14.7.37 OS Lock Status Register
14.7.38 Power Down Control Register
14.7.39 Power Down Status Register
14.7.40 Address Comparator Value Registers, n=0-7
14.7.41 Address Comparator Access Type Registers, n=0-7
14.7.42 Data Value Comparator Value Registers, n=0-1
14.7.43 Data Value Comparator Mask Registers, n=0-1
14.7.44 Context ID Comparator Value Registers 0
14.7.45 Virtual Context Identifier Comparator Value Register
14.7.46 Context ID Comparator Control Register 0
14.7.47 Integration Mode Control Register
14.7.48 Claim Tag Set Register
14.7.49 Claim Tag Clear Register
14.7.50 TRCDEVAFF0, Device Affinity Register 0
14.7.51 TRCDEVAFF1, Device Affinity Register 1
14.7.52 Software Lock Access Register
14.7.53 Software Lock Status Register
14.7.54 Authentication Status Register
14.7.55 Device Architecture Register
14.7.56 Device ID Register
14.7.57 Device Type Register
14.7.58 Peripheral Identification Registers
14.7.59 Component Identification Registers
15 Advanced SIMD and floating-point support
15.1 About the Advanced SIMD and floating-point support
15.2 Floating-point support
15.3 AArch32 single-precision floating point instructions
15.4 Accessing the feature identification registers
15.5 Register summary
15.6 Register descriptions
15.6.1 Floating-point System ID Register
15.6.2 Floating-point Status and Control Register
15.6.3 Media and Floating-point Feature Register 0
15.6.4 Media and Floating-point Feature Register 1
15.6.5 Media and Floating-point Feature Register 2
15.6.6 Floating-Point Exception Control Register
A Signal Descriptions
A.1 Clock and clock enable signals
A.2 Resets
A.3 Reset-related signals
A.4 Configuration inputs
A.5 Memory correcting error reporting signals
A.6 Event output signals
A.7 MRP signals
A.8 Bus interface signals
A.8.1 AXIM interface signals
A.8.2 AXIS interface signals
A.8.3 LLPP interface signals
A.8.4 Flash interface signals
A.9 Debug and trace interface signals
A.9.1 Debug interface signals
A.9.2 ETM interface signals
A.9.3 Cross trigger interface signals
A.10 Generic timer signals
A.11 Power management signals
A.12 DFT and on-line MBIST signals
A.12.1 DFT signals
A.12.2 On-line MBIST signals
A.13 GIC Distributor external messaging port signals
A.14 Interrupt input signals
A.15 DCLS signals
A.16 Split/Lock signal
B Cycle Timings and Interlock Behavior
B.1 About cycle timings and interlock behavior
B.1.1 Pipeline information
B.1.2 Instruction execution overview
B.1.3 Conditional instructions
B.1.4 Flag-setting instructions
B.2 Instructions cycle timings
B.2.1 Definition of terms
B.2.2 Base instructions cycle timings
B.2.3 Floating-point and Advanced SIMD instructions cycle timings
B.3 Pipeline behavior
B.3.1 Skewing
B.3.2 Dual-issuing
B.3.3 Load/store instructions
B.3.4 Division and square root
B.3.5 Floating-point and Advanced SIMD Multiply-Accumulate instructions
B.3.6 Instructions with exceptional behavior
C Processor UNPREDICTABLE Behaviors
C.1 Use of R15 by Instruction
C.2 UNPREDICTABLE instructions within an IT block
C.3 Instruction fetches from Device memory
C.4 Specific UNPREDICTABLE cases for instructions
C.4.1 CLZ
C.4.2 PUSH
C.4.3 RBIT
C.4.4 REV, REV16, REVSH
C.4.5 STC
C.4.6 STM/STMIA/STMEA
C.4.7 STMDA/STMED and STMIB/STMFA
C.4.8 STMDB/STMFD
C.4.9 STR (Immediate, Thumb), STR (Immediate, Arm), STR (register), STRB (immediate, Thumb), STRB (immediate, Arm), STRB (register), STRBT, STRH (immediate, Thumb), STRH (immediate, Arm), STRH (register), STRHT, and STRT
C.4.10 STRD (immediate) and STRD (register)
C.4.11 STREX, STREXB, STREXD, STREXH, STLEX, STLEXB, STLEXD, and STLEXH
C.5 Load/Store accesses crossing MPU regions
C.5.1 Crossing an MPU region with different memory types or shareability attributes
C.5.2 Crossing a 4KB boundary with Device (or Strongly-Ordered) accesses
C.6 Armv8 Debug UNPREDICTABLE behaviors
C.7 Other UNPREDICTABLE behaviors
D Revisions
D.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 12 August 2016 Confidential First release for r0p0.
0100-00 30 March 2017 Non-Confidential First release for r1p0.
0101-00 13 September 2017 Non-Confidential First release for r1p1.
0101-01 16 February 2018 Non-Confidential Second release for r1p1.

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