Arm® Cortex®‑A73 MPCore Processor Technical Reference Manual

Revision r1p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 About the Cortex-A73 processor
1.2 Compliance
1.2.1 Arm® architecture
1.2.2 Interconnect architecture
1.2.3 Generic Interrupt Controller architecture
1.2.4 Generic Timer architecture
1.2.5 Debug architecture
1.2.6 Embedded Trace Macrocell architecture
1.3 Features
1.4 Interfaces
1.5 Main Implementation options
1.5.1 Processor configuration
1.6 Test features
1.7 Product documentation and design flow
1.7.1 Documentation
1.7.2 Design flow
1.8 Product revisions
2 Functional Description
2.1 About the Cortex-A73 processor functions
2.1.1 Instruction side memory system
2.1.2 Integer core
2.1.3 Data side memory system
2.1.4 Memory Management Unit
2.1.5 Advanced SIMD and Floating-point support
2.1.6 Cryptographic Extension
2.1.7 Level 2 memory system
2.1.8 Performance monitoring
2.1.9 Debug and trace
2.2 Interfaces
2.2.1 Master memory interface
2.2.2 Accelerator Coherency Port
2.2.3 External debug interface
2.2.4 Trace interface
2.2.5 Cross Trigger Interface
2.2.6 Design For Test interface
2.2.7 Memory Built-In Self Test interface
2.2.8 Q-channel interface
2.3 Clocking and resets
2.3.1 Clocks
2.3.2 Input synchronization
2.3.3 Resets
2.4 Power management
2.4.1 Power domains
2.4.2 Dynamic Power Management
2.4.3 Power modes
3 Programmers Model
3.1 About the programmers model
3.1.1 Advanced SIMD and Floating-point support
3.1.2 Memory model
3.1.3 Jazelle implementation
3.1.4 Modes of operation
3.2 Armv8-A architecture concepts
3.2.1 Execution state
3.2.2 Exception levels
3.2.3 Security state
3.2.4 Rules for changing execution state
3.2.5 Stack pointer selection
3.2.6 Armv8 security model
3.2.7 Instruction set state
3.2.8 AArch32 execution modes
4 System Control
4.1 About system control
4.2 AArch64 register summary
4.2.1 AArch64 identification registers
4.2.2 AArch64 exception handling registers
4.2.3 AArch64 virtual memory control registers
4.2.4 AArch64 other system control registers
4.2.5 AArch64 cache maintenance operations
4.2.6 AArch64 TLB maintenance operations
4.2.7 AArch64 address translation operations
4.2.8 AArch64 miscellaneous operations
4.2.9 AArch64 performance monitor registers
4.2.10 AArch64 reset registers
4.2.11 AArch64 Secure registers
4.2.12 AArch64 virtualization registers
4.2.13 AArch64 EL2 TLB maintenance operations
4.2.14 AArch64 GIC system registers
4.2.15 AArch64 Generic Timer registers
4.2.16 AArch64 thread registers
4.2.17 AArch64 implementation defined registers
4.2.18 AArch64 implementation defined operations
4.3 AArch64 register descriptions
4.3.1 Main ID Register, EL1
4.3.2 Multiprocessor Affinity Register
4.3.3 Revision ID Register
4.3.4 AArch32 Processor Feature Register 0
4.3.5 AArch32 Processor Feature Register 1
4.3.6 AArch32 Processor Feature Register 2
4.3.7 AArch32 Debug Feature Register 0
4.3.8 AArch32 Auxiliary Feature Register 0
4.3.9 AArch32 Memory Model Feature Register 0
4.3.10 AArch32 Memory Model Feature Register 1
4.3.11 AArch32 Memory Model Feature Register 2
4.3.12 AArch32 Memory Model Feature Register 3
4.3.13 AArch32 Instruction Set Attribute Register 0
4.3.14 AArch32 Instruction Set Attribute Register 1
4.3.15 AArch32 Instruction Set Attribute Register 2
4.3.16 AArch32 Instruction Set Attribute Register 3
4.3.17 AArch32 Instruction Set Attribute Register 4
4.3.18 AArch32 Instruction Set Attribute Register 5
4.3.19 AArch32 Memory Model Feature Register 4
4.3.20 AArch64 Processor Feature Register 0
4.3.21 AArch64 Processor Feature Register 1
4.3.22 AArch64 Debug Feature Register 0, EL1
4.3.23 AArch64 Debug Feature Register 1
4.3.24 AArch64 Auxiliary Feature Register 0
4.3.25 AArch64 Auxiliary Feature Register 1
4.3.26 AArch64 Instruction Set Attribute Register 0, EL1
4.3.27 AArch64 Instruction Set Attribute Register 1, EL1
4.3.28 AArch64 Memory Model Feature Register 0, EL1
4.3.29 AArch64 Memory Model Feature Register 1
4.3.30 Cache Size ID Register
4.3.31 Cache Level ID Register
4.3.32 Auxiliary ID Register
4.3.33 Cache Size Selection Register
4.3.34 Cache Type Register
4.3.35 Data Cache Zero ID Register
4.3.36 Virtualization Processor ID Register
4.3.37 Virtualization Multiprocessor ID Register
4.3.38 System Control Register, EL1
4.3.39 Auxiliary Control Register, EL1
4.3.40 Auxiliary Control Register, EL2
4.3.41 Auxiliary Control Register, EL3
4.3.42 Architectural Feature Access Control Register
4.3.43 System Control Register, EL2
4.3.44 Hypervisor Configuration Register
4.3.45 Hyp Debug Control Register
4.3.46 Architectural Feature Trap Register, EL2
4.3.47 Hyp System Trap Register
4.3.48 Hyp Auxiliary Configuration Register
4.3.49 System Control Register, EL3
4.3.50 Secure Configuration Register
4.3.51 Secure Debug Enable Register
4.3.52 Translation Table Base Register 0, EL1
4.3.53 Translation Table Base Register 1
4.3.54 Architectural Feature Trap Register, EL3
4.3.55 Monitor Debug Configuration Register, EL3
4.3.56 Translation Control Register, EL1
4.3.57 Translation Control Register, EL2
4.3.58 Virtualization Translation Control Register, EL2
4.3.59 Domain Access Control Register
4.3.60 Translation Table Base Register 0, EL3
4.3.61 Translation Control Register, EL3
4.3.62 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
4.3.63 Auxiliary Fault Status Register 0, EL1, EL2 and EL3
4.3.64 Auxiliary Fault Status Register 1, EL1, EL2 and EL3
4.3.65 Exception Syndrome Register, EL1
4.3.66 Instruction Fault Status Register, EL2
4.3.67 Exception Syndrome Register, EL2
4.3.68 Exception Syndrome Register, EL3
4.3.69 Fault Address Register, EL1
4.3.70 Fault Address Register, EL2
4.3.71 Hypervisor IPA Fault Address Register, EL2
4.3.72 L2 Control Register
4.3.73 L2 Extended Control Register
4.3.74 Fault Address Register, EL3
4.3.75 Physical Address Register, EL1
4.3.76 Memory Attribute Indirection Register, EL1
4.3.77 Memory Attribute Indirection Register, EL2
4.3.78 Memory Attribute Indirection Register, EL3
4.3.79 Vector Base Address Register, EL1
4.3.80 Vector Base Address Register, EL2
4.3.81 Vector Base Address Register, EL3
4.3.82 Reset Vector Base Address Register, EL3
4.3.83 Reset Management Register
4.3.84 Interrupt Status Register
4.3.85 Extended Control Register, EL1
4.3.86 L2 Memory Error Syndrome Register
4.3.87 Configuration Base Address Register, EL1
4.3.88 DC CIALL Clean Invalidate All
4.4 AArch32 register summary
4.4.1 c0 registers
4.4.2 c1 registers
4.4.3 c2 registers
4.4.4 c3 registers
4.4.5 c4 registers
4.4.6 c5 registers
4.4.7 c6 registers
4.4.8 c7 registers
4.4.9 c7 System operations
4.4.10 c8 System operations
4.4.11 c9 registers
4.4.12 c10 registers
4.4.13 c11 registers
4.4.14 c12 registers
4.4.15 c13 registers
4.4.16 c14 registers
4.4.17 c15 registers
4.4.18 64-bit registers
4.4.19 AArch32 Identification registers
4.4.20 AArch32 Virtual memory control registers
4.4.21 AArch32 Fault handling registers
4.4.22 AArch32 Other System registers
4.4.23 AArch32 Address translation registers
4.4.24 AArch32 Thread ID registers
4.4.25 AArch32 Performance monitor registers
4.4.26 AArch32 Secure registers
4.4.27 AArch32 Virtualization registers
4.4.28 AArch32 GIC system registers
4.4.29 AArch64 Generic Timer registers
4.4.30 AArch32 Implementation defined registers
4.4.31 AArch32 Implementation defined operations
4.5 AArch32 register descriptions
4.5.1 Main ID Register
4.5.2 Multiprocessor Affinity Register
4.5.3 Revision ID Register
4.5.4 TCM Type Register
4.5.5 TLB Type Register
4.5.6 Processor Feature Register 0
4.5.7 Processor Feature Register 1
4.5.8 Processor Feature Register 2
4.5.9 Debug Feature Register 0
4.5.10 Auxiliary Feature Register 0
4.5.11 Memory Model Feature Register 0
4.5.12 Memory Model Feature Register 1
4.5.13 Memory Model Feature Register 2
4.5.14 Memory Model Feature Register 3
4.5.15 Instruction Set Attribute Register 0
4.5.16 Instruction Set Attribute Register 1
4.5.17 Instruction Set Attribute Register 2
4.5.18 Instruction Set Attribute Register 3
4.5.19 Instruction Set Attribute Register 4
4.5.20 Instruction Set Attribute Register 5
4.5.21 Memory Model Feature Register 4
4.5.22 Cache Size ID Register
4.5.23 Cache Level ID Register
4.5.24 Auxiliary ID Register
4.5.25 Cache Size Selection Register
4.5.26 Cache Type Register
4.5.27 Virtualization Processor ID Register
4.5.28 Virtualization Multiprocessor ID Register
4.5.29 System Control Register
4.5.30 Auxiliary Control Register
4.5.31 Architectural Feature Access Control Register
4.5.32 Secure Configuration Register
4.5.33 Secure Debug Enable Register
4.5.34 Non-Secure Access Control Register
4.5.35 Secure Debug Configuration Register
4.5.36 Hyp Auxiliary Control Register
4.5.37 Hyp System Control Register
4.5.38 Hyp Configuration Register
4.5.39 Hyp Configuration Register 2
4.5.40 Hyp Debug Control Register
4.5.41 Hyp Architectural Feature Trap Register
4.5.42 Translation Table Base Register 0
4.5.43 Translation Table Base Register 1
4.5.44 Translation Table Base Control Register
4.5.45 Hyp Translation Control Register
4.5.46 Virtualization Translation Control Register
4.5.47 Domain Access Control Register
4.5.48 Hyp System Trap Register
4.5.49 Hyp Auxiliary Configuration Register
4.5.50 Data Fault Status Register
4.5.51 Instruction Fault Status Register
4.5.52 Auxiliary Data Fault Status Register
4.5.53 Auxiliary Instruction Fault Status Register
4.5.54 Hyp Auxiliary Data Fault Status Syndrome Register
4.5.55 Hyp Auxiliary Instruction Fault Status Syndrome Register
4.5.56 Hyp Syndrome Register
4.5.57 Data Fault Address Register
4.5.58 Instruction Fault Address Register
4.5.59 Hyp Data Fault Address Register
4.5.60 Hyp Instruction Fault Address Register
4.5.61 Hyp IPA Fault Address Register
4.5.62 Physical Address Register
4.5.63 L2 Control Register
4.5.64 L2 Extended Control Register
4.5.65 Primary Region Remap Register
4.5.66 Memory Attribute Indirection Registers 0 and 1
4.5.67 Normal Memory Remap Register
4.5.68 Auxiliary Memory Attribute Indirection Register 0
4.5.69 Auxiliary Memory Attribute Indirection Register 1
4.5.70 Hyp Auxiliary Memory Attribute Indirection Register 0
4.5.71 Hyp Auxiliary Memory Attribute Indirection Register 1
4.5.72 Vector Base Address Register
4.5.73 Reset Management Register
4.5.74 Interrupt Status Register
4.5.75 Hyp Vector Base Address Register
4.5.76 FCSE Process ID Register
4.5.77 Extended Control Register
4.5.78 L2 Memory Error Syndrome Register
4.5.79 Configuration Base Address Register
4.5.80 DCCIALL Clean Invalidate All
5 Memory Management Unit
5.1 About the MMU
5.2 TLB organization
5.2.1 Instruction micro TLB
5.2.2 Data micro TLB
5.2.3 Main TLB
5.3 TLB match process
5.4 Memory access sequence
5.5 MMU aborts
5.5.1 External aborts
5.5.2 Mis-programming Contiguous Hints
6 Level 1 Memory System
6.1 About the L1 memory system
6.2 Cache behavior
6.3 Support for v8 memory types
6.4 L1 instruction memory system
6.4.1 Instruction cache disabled behavior
6.4.2 Instruction cache speculative memory accesses
6.4.3 Program flow prediction
6.5 L1 data memory system
6.5.1 Data cache coherency
6.5.2 Data cache disabled behavior
6.5.3 Data cache maintenance considerations
6.5.4 Data cache zero
6.5.5 Internal exclusive monitor
6.5.6 ACE transactions
6.6 Memory prefetching
6.6.1 Preload instructions
6.6.2 Data prefetching and monitoring
6.6.3 Non-temporal loads
6.7 Direct access to internal memory
6.7.1 Data cache tag and data encoding
6.7.2 Instruction cache tag and data encoding
6.7.3 TLB data encoding
7 Level 2 Memory System
7.1 About the L2 memory system
7.2 L2 cache
7.2.1 L2 ECC support
7.2.2 L2 cache RAM latency settings
7.3 Snoop Control Unit
7.3.1 Snoop and maintenance requests
7.4 ACE master interface
7.4.1 Memory interface attributes
7.4.2 ACE transfers
7.4.3 Read response
7.4.4 Write response
7.4.5 Barriers
7.4.6 AXI3 compatibility mode
7.4.7 AXI privilege information
7.4.8 AXI ID core source encoding
7.5 Additional memory attributes
7.6 ACP
7.6.1 ACP interface restrictions
7.6.2 ACP requests
7.7 External aborts and asynchronous errors
7.7.1 External aborts
7.7.2 Asynchronous errors
8 Generic Interrupt Controller CPU Interface
8.1 About the Generic Interrupt Controller CPU Interface
8.1.1 Bypassing the CPU Interface
8.2 GIC CPU interface programmers model
8.2.1 Memory map
8.2.2 CPU interface register summary
8.2.3 CPU interface register descriptions
8.2.4 Virtual interface control register summary
8.2.5 Virtual interface control register descriptions
8.2.6 Virtual CPU interface register summary
8.2.7 Virtual CPU interface register descriptions
9 Generic Timer
9.1 About the Generic Timer
9.2 Generic Timer functional description
9.3 Generic Timer register summary
9.3.1 AArch64 Generic Timer register summary
9.3.2 AArch32 Generic Timer register summary
10 Debug
10.1 About debug
10.2 Debug register interfaces
10.2.1 Core interfaces
10.2.2 Breakpoints and watchpoints
10.2.3 Effects of resets on debug registers
10.2.4 External access permissions
10.3 AArch64 debug register summary
10.4 AArch64 debug register descriptions
10.4.1 Debug Breakpoint Control Registers, EL1
10.4.2 Debug Watchpoint Control Registers, EL1
10.5 AArch32 debug register summary
10.6 AArch32 debug register descriptions
10.6.1 Debug ID Register
10.6.2 Debug Device ID Register
10.6.3 Debug Device ID Register 1
10.7 Memory-mapped debug register summary
10.8 Memory-mapped debug register descriptions
10.8.1 External Debug Reserve Control Register
10.8.2 External Debug Device ID Register 0
10.8.3 External Debug Device ID Register 1
10.8.4 External Debug Peripheral Identification Registers
10.8.5 External Debug Component Identification Registers
10.9 Debug events
10.9.1 Watchpoint debug events
10.9.2 Debug OS Lock
10.10 External debug interface
10.10.1 Debug memory map
10.10.2 DBGPWRDUP debug signal
10.10.3 DBGL1RSTDISABLE debug signal
10.10.4 Changing the authentication signals
10.11 ROM table
10.11.1 ROM table register summary
10.11.2 ROM table register descriptions
10.11.3 ROM table Debug Peripheral Identification Registers
10.11.4 ROM tables Debug Component Identification Registers
11 Performance Monitor Unit
11.1 About the PMU
11.2 PMU functional description
11.2.1 External register access permissions
11.3 AArch64 PMU register summary
11.4 AArch64 PMU register descriptions
11.4.1 Performance Monitors Control Register
11.4.2 Performance Monitors Common Event Identification Register 0
11.4.3 Performance Monitors Common Event Identification Register 1
11.5 AArch32 PMU register summary
11.6 AArch32 PMU register descriptions
11.6.1 Performance Monitors Control Register
11.6.2 Performance Monitors Common Event Identification Register 0
11.6.3 Performance Monitors Common Event Identification Register 1
11.7 Memory-mapped PMU register summary
11.8 Memory-mapped PMU register descriptions
11.8.1 Performance Monitors Configuration Register
11.8.2 Performance Monitors Peripheral Identification Registers
11.8.3 Performance Monitors Component Identification Registers
11.9 Events
11.10 Interrupts
11.11 Exporting PMU events
11.11.1 External hardware
11.11.2 Debug trace hardware
12 Embedded Trace Macrocell
12.1 About the ETM
12.2 ETM trace unit generation options and resources
12.3 ETM trace unit functional description
12.4 Reset
12.5 Modes of operation and execution
12.5.1 Controlling ETM trace unit programming
12.5.2 Programming and reading ETM trace unit registers
12.6 ETM trace unit register interfaces
12.6.1 Access permissions
12.7 ETM register summary
12.8 ETM register descriptions
12.8.1 Trace Configuration Register
12.8.2 Auxiliary Control Register
12.8.3 Event Control 0 Register
12.8.4 Event Control 1 Register
12.8.5 Stall Control Register
12.8.6 Global Timestamp Control Register
12.8.7 Synchronization Period Register
12.8.8 Cycle Count Control Register
12.8.9 Branch Broadcast Control Register
12.8.10 Trace ID Register
12.8.11 ViewInst Main Control Register
12.8.12 ViewInst Include-Exclude Control Register
12.8.13 ViewInst Start-Stop Control Register
12.8.14 Sequencer State Transition Control Registers 0-2
12.8.15 Sequencer Reset Control Register
12.8.16 Sequencer State Register
12.8.17 External Input Select Register
12.8.18 Counter Reload Value Registers 0-1
12.8.19 Counter Control Register 0
12.8.20 Counter Control Register 1
12.8.21 Counter Value Registers 0-1
12.8.22 ID Register 8
12.8.23 ID Register 9
12.8.24 ID Register 10
12.8.25 ID Register 11
12.8.26 ID Register 12
12.8.27 ID Register 13
12.8.28 Implementation Specific Register 0
12.8.29 ID Register 0
12.8.30 ID Register 1
12.8.31 ID Register 2
12.8.32 ID Register 3
12.8.33 ID Register 4
12.8.34 ID Register 5
12.8.35 Resource Selection Control Registers 2-16
12.8.36 Single-Shot Comparator Control Register 0
12.8.37 Single-Shot Comparator Status Register 0
12.8.38 Address Comparator Value Registers 0-7
12.8.39 Address Comparator Access Type Registers 0-7
12.8.40 Context ID Comparator Value Register 0
12.8.41 VMID Comparator Value Register 0
12.8.42 Context ID Comparator Control Register 0
12.8.43 Integration ATB Identification Register
12.8.44 Integration Instruction ATB Data Register
12.8.45 Integration Instruction ATB In Register
12.8.46 Integration Instruction ATB Out Register
12.8.47 Integration Mode Control Register
12.8.48 Claim Tag Set Register
12.8.49 Claim Tag Clear Register
12.8.50 Device Affinity Register 0
12.8.51 Device Affinity Register 1
12.8.52 Peripheral Identification Registers
12.9 Interaction with Debug and Performance Monitoring Unit
12.9.1 Interaction with the Performance Monitoring Unit
12.9.2 Effect of Debug double lock on trace register access
13 Cross Trigger
13.1 About the cross trigger
13.2 Trigger inputs and outputs
13.3 Cortex-A73 CTM
13.4 Cross trigger register summary
13.4.1 External register access permissions
13.5 Cross trigger register descriptions
13.5.1 CTI Device Identification Register
13.5.2 CTI Integration Mode Control Register
13.5.3 CTI Peripheral Identification Registers
13.5.4 Component Identification Registers
14 Advanced SIMD and Floating-point Support
14.1 About the Advanced SIMD and Floating-point support
14.2 Floating-point support
14.3 Accessing the feature identification registers
14.4 AArch64 register summary
14.5 AArch64 register descriptions
14.5.1 Floating-point Control Register
14.5.2 Floating-point Status Register
14.5.3 Media and VFP Feature Register 0, EL1
14.5.4 Media and VFP Feature Register 1, EL1
14.5.5 Media and VFP Feature Register 2, EL1
14.5.6 Floating-point Exception Control Register 32, EL2
14.6 AArch32 register summary
14.7 AArch32 register descriptions
14.7.1 Floating-point System ID Register
14.7.2 Floating-point Status and Control Register
14.7.3 Media and Floating-point Feature Register 0
14.7.4 Media and Floating-point Feature Register 1
14.7.5 Media and Floating-point Feature Register 2
14.7.6 Floating-Point Exception Control Register
A Signal Descriptions
A.1 About the signal descriptions
A.2 Clock signals
A.3 Reset signals
A.4 Configuration signals
A.5 Generic Interrupt Controller signals
A.6 Generic Timer signals
A.7 Power management signals
A.8 L2 error signals
A.9 ACE interface signals
A.9.1 Clock and configuration signals
A.9.2 Write address channel signals
A.9.3 Write data channel signals
A.9.4 Write data response channel signals
A.9.5 Read address channel signals
A.9.6 Read data channel signals
A.9.7 Coherency address channel signals
A.9.8 Coherency response channel signals
A.9.9 Coherency data channel handshake signals
A.9.10 Read and write acknowledge signals
A.10 ACP interface signals
A.10.1 Clock and configuration signals
A.10.2 Write address channel signals
A.10.3 Write data channel signals
A.10.4 Write response channel signals
A.10.5 Read address channel signals
A.10.6 Read data channel signals
A.11 External debug interface
A.11.1 APB interface signals
A.11.2 Miscellaneous debug signals
A.12 ATB interface signals
A.13 Miscellaneous ETM trace unit signals
A.14 CTI interface signals
A.15 PMU interface signals
A.16 DFT and MBIST interface signals
A.16.1 DFT interface
A.16.2 MBIST interface
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-01 23 June 2015 Confidential First release for r0p0
0001-02 27 October 2015 Confidential First release for r0p1
0002-03 10 March 2016 Confidential First release for r0p2
0002-04 03 June 2016 Non-Confidential Second release for r0p2
0002-05 10 August 2016 Non-Confidential Third release for r0p2
0100-06 21 June 2018 Non-Confidential First release for r1p0

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