2.5.2 Microarchitectural QoS support

The CCN-502 provides QoS support.

The following subsections describe the QoS support that the CCN-502 components provide:

QoS regulators

This section describes QoS regulators.

The QPV of RN requests must be modulated depending on how the respective QoS requirements are met. Although the QoS-modulation capability can be integrated into the RN, the CCN-502 enables system designers to include non-QoS-aware devices in the CCN-502 system, but still have these devices meet the QoS-modulation requirements of the CCN-502 QoS microarchitecture.

The CCN-502 includes inline QoS regulators that perform QoS modulation without requiring any QoS-awareness by the requesting device. A QoS regulator introduces an interstitial layer between an RN and the interconnect that monitors whether the bandwidth and latency requirements of the RN are being met. It also performs in-line replacement of the RN-provided QPV field as required, adjusting upwards to increase priority or downwards to reduce priority in the system.

The QoS regulators are present at all entry points into the CCN-502:

  • For CHI ports, the regulator is present in the XP.
  • For AMBA slave interfaces, the regulator is present at the AMBA side of the protocol bridge.

Therefore, for AMBA interfaces there are two QoS regulators:

  • One in the XP at the CHI side of the protocol bridge.
  • One in the protocol bridge at the AMBA interface.

For AMBA interfaces, the XP QoS regulator must be configured to operate in a pass-through mode, so that only the AMBA-side regulator performs active regulation.

The CCN-502 QoS regulators have three operating modes, controlled through memory-mapped configuration registers:

  1. Pass-through.
  2. Programmed QoS value.
  3. Regulation.

QoS regulator operation

The values of the base QPV, AxQOS for AMBA interfaces or REQ.QOS for CHI ports, are input to the QoS sub-block. When latency regulation or period regulation is enabled, these values are replaced by the AxQOS or REQ.QOS values generated by the regulators. For CHI RN-Fs, the one QoS regulator monitors read-type CHI transactions, and the resultant QPV is applied to all CHI requests. For RN-Is, separate QoS regulators exist for AR and AW channels.

The QoS regulators can operate in either latency regulation mode or period regulation mode. The registers to configure the QoS regulators exist in each RN-I and XP.

The following sections describe operating modes for slave interface S0 in the RN-I.

Latency regulation mode
When configured for latency regulation, the QoS regulator increases the QPV whenever actual latency is higher than the target, and decreases the QPV when it is lower:
  • For every cycle that the latency of a transaction is more than the target latency, the QPV is increased by a fractional amount, the scale factor Ki.
  • For every cycle that latency of a transaction is less than the target latency, the QPV is decreased by the same fractional amount, the scale factor Ki.

The Port 0 QoS Latency Target register specifies the target latency in cycles.

The Port 0 QoS Latency Scale register specifies the scale factor Ki. It is coded in powers of two, so that a programmed value of 0x0 = 2-12 and a programmed value of 0x7 = 2-5.

You can program the QoS regulator to operate in latency regulation mode by programming the following bits in the Port 0 QoS Control register:

  • Set the s0_ar_qos_override_en bit to 1.
  • Set the s0_ar_lat_en bit to 1.
  • Set the s0_ar_reg_mode bit to 0.
  • Set the s0_ar_pqv_mode bit to 0.
Period regulation mode for bandwidth regulation
When configured for period regulation, the QoS regulator increases the QPV whenever the period between transactions is larger than the target, and decreases the QPV when it is lower:
  • For every cycle that the period between transactions is more than the target period, the QPV is increased by a fractional amount, the scale factor Ki.
  • For every cycle that the period between transactions is less than the target period, the QPV is decreased by the same fractional amount, the scale factor Ki.

The Port 0 QoS Latency Target register specifies the target period in cycles.

The Port 0 QoS Latency Scale register specifies the scale factor Ki. It is coded in powers of two, so that a programmed value of 0x0 = 2-12 and a programmed value of 0x7 = 2-5.

You can program the QoS regulator to operate in period regulation mode by programming the following bits in the Port 0 QoS Control register:

  • Set the s0_ar_qos_override_en bit to 1.
  • Set the s0_ar_lat_en bit to 1.
  • Set the s0_ar_reg_mode bit to 1.

There are two modes of period regulation:

  • In normal mode, the QPV neither increases nor decreases when there are zero outstanding transactions.
  • In quiesce high mode, the QPV increases by a fractional amount, the scale factor Ki, in every cycle where there are zero outstanding transactions.

Select the mode of period regulation by programming the s0_ar_pqv_mode bit in the Port 0 QoS Control register.

Note:

The example shows the register names for the Port 0 RN-I bridge. The QoS register names for the XP are similar but use a dev0_ and dev1_ prefix.

Ring/XP QoS support

This section describes Ring/XP QoS support.

In addition to the integrated QoS regulators, the XP includes support for prioritized arbitration.

The XP includes a general starvation prevention mechanism to ensure that all devices make forward progress. This includes an upload and a download starvation prevention mechanism.

Upload starvation mechanism

When sending a flit from a device onto the ring during an upload, and the flit cannot be uploaded for a number of cycles defined by the upload_starv_thresh value in the XP Auxiliary Control register, the mechanism assigns a ring-slot for use only by the starving device.

When that slot becomes free, that is, when its current flit has been downloaded, the slot is only used by the starving device, guaranteeing that the starving device makes forward progress. When the qpc_en bit of the Auxiliary Control register is set, for requests with the highest QPV value, that is, QPV==15, the slot is assigned immediately if the flit is not able to upload, without waiting for the flit age to reach the defined starvation threshold. This effectively prioritizes QoS-15 requests over other requests.

Download starvation mechanism

When sending a flit from the ring to the device during a download, and the flit cannot download for a number of cycles defined by the dnload_starv_thresh value in the XP Auxiliary Control register, the mechanism sets a bit in the download port of the relevant XP. This reserves a flit-buffer for use only by the starving device.

When that buffer becomes free, that is, when its current flit has been sent to the device, the buffer is only used by the starving flit, guaranteeing that the starving flit makes forward progress. When the qpc_en bit of the Auxiliary Control register is set, for requests with the highest QPV value, that is, QPV==15, this bit is set immediately if the flit is not able to download, without waiting for the flit age to reach the defined starvation threshold. This effectively prioritizes QoS-15 requests over other requests.

HN-F QoS support

The HN-F is a key shared system resource used for system caching and for communication with the memory controller for external memory access. It includes the following QoS support mechanisms:

QoS decoding in HN-F

The HN-F interprets the 4-bit QPV at a coarser granularity, as the following table shows.

Table 2-1 QoS classes in HN-F

QoS value range QoS Class Class mnemonic Priority
15 HighHigh HH Highest
14-12 High H High
11-8 Med M Medium
7-0 Low L Low
QoS class and POCQ resource availability

The HN-F includes a 32-entry (6XP/2HNF) or 16/32-entry option (8XP/4HNF) structure, the Point-of-Coherency Queue (POCQ), from which all transaction ordering and scheduling is performed. The POCQ buffers are shared resources for all QoS classes, with one entry being reserved for internal use. The higher the QoS class, the higher the occupancy availability. As the following figure shows, the POCQ is partitioned so that higher priority requests are able to use a larger percentage of the POCQ buffering, ensuring bandwidth and latency requirements of higher priority transactions are met. The QoS bands change depending on which configuration option is selected. The configuration format is: [32] Param HNF POCQ_NUM_ENTRIES_PARAM // NUM POCQ ENTRIES [16/32]

The number of entries available for use by each QoS class is defined in the HN-F QoS Reservation register, and is software-programmable.

Figure 2-4 POCQ availability and QoS classes
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The QoS pools are:

hh_pool

Available for HH class.

h_pool

Available for H class and HH class.

m_pool

Available for M class, H class, and HH class.

l_pool

Available for all classes.

seq

Snoop filter evictions only.

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