3.3.3 HN-F register descriptions

Lists the HN-F registers.

HN-F Configuration Control register

The hnf_cfg_ctrl register is at offset 0x0000. Its characteristics are:

PurposeControls the HN-F configuration.
Usage constraintsOnly accessible by Secure accesses. Writes to this register must be complete before the first non-configuration access targeting the HN-F.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the hnf_cfg_ctrl register bit assignments.

Figure 3-60 hnf_cfg_ctrl register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hnf_cfg_ctrl register bit assignments.

Table 3-74 hnf_cfg_ctrl register bit assignments

Bits Name Access Reset value Function
[63:21] - RAZ/WI 0x0 Reserved
[20] ncdevcmo_mc_comp RW 0

Disable HN-F completion. The HN-F sends completion for the following transactions after receiving completion from SN-F:

  • Non-cacheable WriteNoSnp.
  • Device WriteNoSnp.
  • Cache Maintenance Operations (CMOs).
[19] - RAZ/WI 0 Reserved
[18] sf_ecc_scrub_disable RW 0 Disable SF tag single-bit ECC error scrubbing.
[17] l3_dat_ecc_scrub_disable RW 0 Disable L3 data single-bit ECC error scrubbing.
[16] l3_tag_ecc_scrub_disable RW 0 Disable L3 tag single-bit ECC error scrubbing.
[15] - RAZ/WI 0b0 Reserved
[14] pois_dis RW 0 Disable parity error data poisoning.
[13] par_err_dis RW 0 Disable parity error interrupt signaling.
[12:9] Reserved RAZ/WI 0x0 -
[8] cg_disable RW 0 Disable HN-F architectural clock gates.
[7:5] - RAZ/WI 0x0 Reserved
[4] ecc_disable RW 0 Disable L3 and SF ECC generation and detection.
[3:0] - RAZ/WI 0x0 Reserved

HN-F SAM Control register

The hnf_sam_control register is at offset 0x0008. Its characteristics are:

PurposeControls the HN-F System Address Map (SAM).
Usage constraintsOnly accessible by Secure accesses. Writes to this register must be complete before any non-configuration access targets the HN-F.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the hnf_sam_control register bit assignments.

Figure 3-61 hnf_sam_control register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hnf_sam_control register bit assignments.

Table 3-75 hnf_sam_control register bit assignments

Bits Name Access Reset value Function
[63:62] - RAZ/WI 0x0 Reserved
[61:56] hn_cfg_sam_top_address_bit1 RW 0x0 Number for the bit position of the top[1] physical address bit of DRAM, which is used by the 3 SN routing mechanism. Permitted values are 28-43 inclusive.
[55:54] - RAZ/WI 0b00 Reserved
[53:48] hn_cfg_sam_top_address_bit0 RW 0x0 Number for the bit position of the top[0] physical address bit of DRAM, which is used by the 3 SN routing mechanism. Permitted values are 28-43 inclusive.
[47:33] - RAZ/WI 0x0 Reserved
[32] hn_cfg_three_sn_en RW 0b0 Enable for 3 SN mode. Set to 1 to enable routing to three SNs.
[31:23] - RAZ/WI 0x0 Reserved
[22:16] hn_cfg_sn2_nodeid RW Value depends on HN-F Node ID for slave node 2. This field is only valid when hn_cfg_three_sn_en=1.
[15] - RAZ/WI 0 Reserved
[14:8] hn_cfg_sn1_nodeid RW 0x0 Node ID for slave node 1. This field is only valid when hn_cfg_three_sn_en=1.
[7] - RAZ/WI 0 Reserved
[6:0] hn_cfg_sn0_nodeid RW Value depends on HN-F Node ID for slave node 0.

HN-F P-state Request register

The hn_cfg_pstate_req register is at offset 0x0010. Its characteristics are:

PurposeControls the HN-F P-state requests.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the hn_cfg_pstate_req register bit assignments.

Figure 3-62 hn_cfg_pstate_req register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hn_cfg_pstate_req register bit assignments.

Table 3-76 hn_cfg_pstate_req register bit assignments

Bits Name Access Reset value Function
[63:2] - RAZ/WI 0x0 Reserved
[1:0] pstate WO 0b00

P-state request:

0b00HNF_PM_NOL3.
0b01HNF_PM_SFONLY.
0b10HNF_PM_HALF.
0b11HNF_PM_FULL.

HN-F P-state Status register

The hn_cfg_pstate_status register is at offset 0x0018. Its characteristics are:

PurposeIndicates the HN-F P-state status.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the hn_cfg_pstate_status register bit assignments.

Figure 3-63 hn_cfg_pstate_status register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hn_cfg_pstate_status register bit assignments.

Table 3-77 hn_cfg_pstate_status register bit assignments

Bits Name Access Reset value Function
[63:6] - RAZ/WI 0x0 Reserved
[5:4] retention RO 0b00

P-state retention status:

0b00HNF_PM_RET_IDLE.
0b01HNF_PM_RET_IDLE_2_RET.
0b10HNF_PM_RET_RET.
0b11HNF_PM_RET_RET_2_IDLE.
[3:0] pstate RO 0x0

P-state status:

0b0000HNF_PM_NOL3.
0b0001HNF_PM_NOL3_2_SFONLY.
0b0010HNF_PM_NOL3_2_HALF.
0b0011HNF_PM_NOL3_2_FULL.
0b0100HNF_PM_SFONLY.
0b0101HNF_PM_SFONLY_2_NOL3.
0b0110HNF_PM_SFONLY_2_HALF.
0b0111HNF_PM_SFONLY_2_FULL.
0b1000HNF_PM_HALF.
0b1001HNF_PM_HALF_2_NOL3.
0b1010HNF_PM_HALF_2_SFONLY.
0b1011HNF_PM_HALF_2_FULL.
0b1100HNF_PM_FULL.
0b1101HNF_PM_FULL_2_NOL3.
0b1110HNF_PM_FULL_2_SFONLY.
0b1111HNF_PM_FULL_2_HALF.

QoS Band register

The qos_band register indicates the QoS classifications based on the QoS value ranges.

The qos_band register is at offset 0x0020. Its characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the qos_band register bit assignments.

Figure 3-64 qos_band register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the qos_band register bit assignments.

Table 3-78 qos_band register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:28] highhigh_max_qos_val RO 0xF Highest QoS class: Maximum value
[27:24] highhigh_min_qos_val RO 0xF Highest QoS class: Minimum value
[23:20] high_max_qos_val RO 0xE High QoS class: Maximum value
[19:16] high_min_qos_val RO 0xC High QoS class: Minimum value
[15:12] med_max_qos_val RO 0xB Medium QoS class: Maximum value
[11:8] med_min_qos_val RO 0x8 Medium QoS class: Minimum value
[7:4] low_max_qos_val RO 0x7 Low QoS class: Maximum value
[3:0] low_min_qos_val RO 0x0 Low QoS class: Minimum value

QoS Reservation register

The qos_reservation register is at offset 0x0028. Its characteristics are:

PurposeSelects the POCQ maximum occupancy counts for each QoS class, that is, highest, high, medium, and low.
Usage constraintsWrites to this register must be complete before the first non-configuration access to the HN-F.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the qos_reservation register bit assignments.

Figure 3-65 qos_reservation register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the qos_reservation register bit assignments.

Table 3-79 qos_reservation register bit assignments

Bits Name Access Reset value Function
[63:37] - RAZ/WI 0x0 Reserved
[36:32] seq_qos_max_cnt RW 0x01 Number of entries that are reserved for snoop filter evictions in POCQ. Must be 1.
[31:29] - RAZ/WI 0x0 Reserved
[28:24] highhigh_qos_max_cnt RW 0x1F Maximum number of highest QoS class occupancy. Allowed range is 5-31.
[23:21] - RAZ/WI 0x0 Reserved
[20:16] high_qos_max_cnt RW 0x1E Maximum number of high QoS class occupancy. Allowed range is 4 - (highhigh_qos_max_cnt–1).
[15:13] - RAZ/WI 0x0 Reserved
[12:8] med_qos_max_cnt RW 0x0F Maximum number of medium QoS class occupancy. Allowed range is 3 - (high_qos_max_cnt–1).
[7:5] - RAZ/WI 0x0 Reserved
[4:0] low_qos_max_cnt RW 0x05 Maximum number of low QoS class occupancy. Allowed range is 2 - (med_qos_max_cnt–1).

RN Starvation register

The rn_starvation register is at offset 0x0030. Its characteristics are:

PurposeSelects the starvation counts for various QoS classes for static credit grantee selection.
Usage constraintsWrites to this register must be complete before the first non-configuration access to the HN-F.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the rn_starvation register bit assignments.

Figure 3-66 rn_starvation register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the rn_starvation register bit assignments.

Table 3-80 rn_starvation register bit assignments

Bits Name Access Reset value Function
[63:45] - RAZ/WI 0x0 Reserved
[44:40] rn_high_over_high_high_max_cnt RW 0x1F Maximum number of consecutive times highest QoS class win over high QoS class
[39:38] - RAZ/WI 0x0 Reserved
[37:32] rn_med_over_highhigh_max_cnt RW 0x3F Maximum number of consecutive times highest QoS class win over medium QoS class
[31:29] - RAZ/WI 0x0 Reserved
[28:24] rn_med_over_high_max_cnt RW 0x1F Maximum number of consecutive times high QoS class win over medium QoS class
[23] - RAZ/WI 0 Reserved
[22:16] rn_low_over_highhigh_max_cnt RW 0x3F Maximum number of consecutive times highest QoS class win over low QoS class
[15:14] - RAZ/WI 0x0 Reserved
[13:8] rn_low_over_high_max_cnt RW 0x3F Maximum number of consecutive times high QoS class win over low QoS class
[7:5] - RAZ/WI 0x0 Reserved
[4:0] rn_low_over_med_max_cnt RW 0x1F Maximum number of consecutive times medium QoS class win over low QoS class

HN-F Error Injection Enable and Setup register

The hnf_err_inj register is at offset 0x0038. Its characteristics are:

PurposeError injection enable and setup register. When enabled for a specific SrcID and LPID, the HN-F returns a slave error and reports an error interrupt through the MN to emulate an L3 double bit data ECC error. This feature enables software to test the error handler. A slave error is reported for a cacheable read access when an L3 hit is the source of the data. For a cacheable read access that results in an L3 miss, no slave error or error interrupt is reported.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the hnf_err_inj register bit assignments.

Figure 3-67 hnf_err_inj register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hnf_err_inj register bit assignments.

Table 3-81 hnf_err_inj register bit assignments

Bits Name Access Reset value Function
[63:23] - RAZ/WI 0x0 Reserved
[22:16] hnf_err_inj_srcid RW 0x0 SrcID read access that results in an L3 miss, with no slave error or error to match for HN-F error injection
[15:7] - RAZ/WI 0x0 Reserved
[6:4] hnf_err_inj_lpid RW 0x0 LPID to match for HN-F error injection
[3:1] - RAZ/WI 0x0 Reserved
[0] hnf_err_inj_en RW 0 HN-F error injection and report enable

HN-F L3 Lock Ways register

The hnf_l3_lock_ways register is at offset 0x0040. Its characteristics are:

PurposeControls the number of locked HN-F L3 ways. This can be a value of 1, 2, 4, 8, or 12.
Usage constraintsOnly accessible by Secure accesses. The L3 must be flushed before writing this register, and no non-configuration accesses to the HN-F can be in-flight while the write to this register is occurring.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the bit assignments.

Figure 3-68 hnf_l3_lock_ways register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-82 hnf_l3_lock_ways register bit assignments

Bits Name Access Reset value Function
[63:4] - RAZ/WI 0x0 Reserved
[3:0] ways RW 0x0 Number of ways locked

HN-F L3 Lock Base 0 register

The hnf_l3_lock_base0 register is at offset 0x0048. Its characteristics are:

PurposeBase register for lock range 0 [43:0].
Usage constraintsOnly accessible by Secure accesses. The L3 must be flushed before writing this register, and no non-configuration accesses to the HN-F can be in-flight while the write to this register is occurring.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the bit assignments.

Figure 3-69 hnf_l3_lock_base0 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-83 hnf_l3_lock_base0 register bit assignments

Bits Name Access Reset value Function
[63] base0_vld RW 0 Lock base 0 valid
[62:44] - RAZ/WI 0x0 Reserved
[43:0] base0 RW 0x0 Lock base 0

HN-F L3 Lock Base 1 register

The hnf_l3_lock_base1 register is at offset 0x0050. Its characteristics are:

PurposeBase register for lock range 1 [43:0].
Usage constraintsOnly accessible by Secure accesses. The L3 must be flushed before writing this register, and no non-configuration accesses to the HN-F can be in-flight while the write to this register is occurring.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the bit assignments.

Figure 3-70 hnf_l3_lock_base1 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-84 hnf_l3_lock_base1 register bit assignments

Bits Name Access Reset value Function
[63] base1_vld RW 0 Lock base 1 valid
[62:44] - RAZ/WI 0x0 Reserved
[43:0] base1 RW 0x0 Lock base 1

HN-F L3 Lock Base 2 register

The hnf_l3_lock_base2 register is at offset 0x0058. Its characteristics are:

PurposeBase register for lock range 2 [43:0].
Usage constraintsOnly accessible by Secure accesses. The L3 must be flushed before writing this register, and no non-configuration accesses to the HN-F can be in-flight while the write to this register is occurring.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the bit assignments.

Figure 3-71 hnf_l3_lock_base2 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-85 hnf_l3_lock_base2 register bit assignments

Bits Name Access Reset value Function
[63] base2_vld RW 0 Lock base 2 valid
[62:44] - RAZ/WI 0x0 Reserved
[43:0] base2 RW 0x0 Lock base 2

HN-F L3 Lock Base 3 register

The hnf_l3_lock_base3 register is at offset 0x0060. Its characteristics are:

PurposeBase register for lock range 3 [43:0].
Usage constraintsOnly accessible by Secure accesses. The L3 must be flushed before writing this register, and no non-configuration accesses to the HN-F can be in-flight while the write to this register is occurring.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the bit assignments.

Figure 3-72 hnf_l3_lock_base3 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-86 hnf_l3_lock_base3 register bit assignments

Bits Name Access Reset value Function
[63] base3_vld RW 0 Lock base 3 valid
[62:44] - RAZ/WI 0x0 Reserved
[43:0] base3 RW 0x0 Lock base 3

HN-F Byte Parity Error Injection register

The hnf_byte_par_err_inj register is at offset 0x0068. Its characteristics are:

PurposeSelects a byte lane, within the 128-bit data bus, and injects a byte parity error on the DAT flits when the next L3 hit occurs.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the hnf_byte_par_err_inj register bit assignments.

Figure 3-73 hnf_byte_par_err_inj register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hnf_byte_par_err_inj register bit assignments.

Table 3-87 byte_par_err_inj register bit assignments

Bits Name Access Reset value Function
[63:4] - RAZ/WI 0x0 Reserved.
[3:0] hnf_byte_par_err_inj WO -

The value selects a byte lane within the 128-bit data bus. The CCN injects a byte parity error on the chosen byte lane in 4 DAT flits, when the next L3 hit occurs.

The bit values are:

0b0000Inserts a parity error in bits[7:0].
0b0001Inserts a parity error in bits[15:8].
0b0010Inserts a parity error in bits[23:16].
0b1111Inserts a parity error in bits[127:120].

If multiple writes occur to this field before the HN-F generates the 4 DAT flits, then the HN-F uses the initial value that is written and ignores the subsequent writes.

HN Configuration RN-I Vector register

The hn_cfg_rni_vec register is at offset 0x0108. Its characteristics are:

PurposeIndicates which SrcIDs are RN-I protocol nodes.
Usage constraintsWrites to this register must be complete before the first coherent access to the HN-F.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the hn_cfg_rni_vec register bit assignments.

Figure 3-74 hn_cfg_rni_vec register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hn_cfg_rni_vec register bit assignments.

Table 3-88 hn_cfg_rni_vec register bit assignments

Bits Name Access Reset value Function
[63:0] rni_vec RW Value depends on customer configuration Bit vector representing all the RN-I NodeIDs

Snoop Domain Control register

The snoop_domain_ctl register is at offset 0x0200. Its characteristics are:

PurposeDetermines the RN-F targets for snoops. Every RN-F node that is actively participating in cache coherence has its respective bit set. If the bit is clear, the corresponding RN-F node is not snooped.
Usage constraintsThis register must be configured correctly, using the snoop_domain_ctl_set and snoop_domain_ctl_clr registers, before the first coherent access to the HN-F.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the snoop_domain_ctl register bit assignments.

Figure 3-75 snoop_domain_ctl register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the snoop_domain_ctl register bit assignments.

Table 3-89 snoop_domain_ctl register bit assignments

Bits Name Access Reset value Function
[63:0] snoop_domain_ctl RO 0x0 Bit vector representing RN-F nodes that can be snooped

Snoop Domain Control Set register

The snoop_domain_ctl_set register is at offset 0x0210. Its characteristics are:

PurposeInserts RN-Fs into the active snoop domain, setting the corresponding bit in the snoop_domain_ctl register, and causing the RN-Fs to receive and requiring response to snoops.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the snoop_domain_ctl_set register bit assignments.

Figure 3-76 snoop_domain_ctl_set register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the snoop_domain_ctl_set register bit assignments.

Table 3-90 snoop_domain_ctl_set register bit assignments

Bits Name Access Reset value Function
[63:0] snoop_domain_ctl_set WO 0x0 Bit vector indicating the NodeIDs of the RN-Fs to be inserted into the active snoop domain

Snoop Domain Control Clear register

The snoop_domain_ctl_clr register is at offset 0x0220. Its characteristics are:

PurposeRemoves RN-Fs from the active snoop domain, clearing the corresponding bit in the snoop_domain_ctl register, and causing the RN-Fs to no longer receive or be allowed to respond to snoops.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the snoop_domain_ctl_clr register bit assignments.

Figure 3-77 snoop_domain_ctl_clr register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the snoop_domain_ctl_clr register bit assignments.

Table 3-91 snoop_domain_ctl_clr register bit assignments

Bits Name Access Reset value Function
[63:0] snoop_domain_ctl_clr WO 0x0 Bit vector indicating the NodeIDs of the RN-Fs to be removed from the active snoop domain

HN Debug Read Configuration register

The hn_cfg_l3sf_dbgrd register is at offset 0x0300. Its characteristics are:

PurposeControls access to the L3 tag, data, and snoop filter.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the hn_cfg_l3sf_dbgrd register bit assignments.

Figure 3-78 hn_cfg_l3sf_dbgrd register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hn_cfg_l3sf_dbgrd register bit assignments.

Table 3-92 hn_cfg_l3sf_dbgrd register bit assignments

Bits Name Access Reset value Function
[63:26] - RAZ/WI 0x0 Reserved
[25:24] l3_access_component WO 0b00 L3/SF debug read array specifier:
0b01L3 data read.
0b10L3 tag read.
0b11SF tag read.
[23] - RAZ/WI 0 Reserved
[22:20] l3_access_ow WO 0x0 64-bit chunk address for L3 data debug read access.
[19:16] l3_access_way WO 0x0 Way address for L3/SF debug read access.
[15:12] - RAZ/WI 0x0 Reserved
[11:0] l3_access_set WO 0x0 Set address for L3/SF debug read access.

Note:

If a debug read is performed to an array entry that has not yet been initialized or written, the value of the data that is returned is indeterminate.

L3 Cache Access Tag register

The l3_cache_access_l3_tag register is at offset 0x0308. Its characteristics are:

PurposeIndicates L3 cache tag storage.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the l3_cache_access_l3_tag register bit assignments.

Figure 3-79 l3_cache_access_l3_tag register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the l3_cache_access_l3_tag register bit assignments.

Table 3-93 l3_cache_access_l3_tag register bit assignments

Bits Name Access Reset value Function
[63:44] - RAZ/WI 0x0 Reserved
[43:0] l3_cache_access_l3_tag RO 0x0 L3 tag debug read data register

L3 Cache Access Data register

The l3_cache_access_l3_data register is at offset 0x0310. Its characteristics are:

PurposeIndicates L3 cache data storage.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the l3_cache_access_l3_data register bit assignments.

Figure 3-80 l3_cache_access_l3_data register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the l3_cache_access_l3_data register bit assignments.

Table 3-94 l3_cache_access_l3_data register bit assignments

Bits Name Access Reset value Function
[63:0] l3_cache_access_l3_data RO 0x0 L3 data debug read data register

L3 Cache Access SF Tag register

The l3_cache_access_sf_tag register is at offset 0x0318. Its characteristics are:

PurposeIndicates L3 cache SF tag storage.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the l3_cache_access_sf_tag register bit assignments.

Figure 3-81 l3_cache_access_sf_tag register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the l3_cache_access_sf_tag register bit assignments.

Table 3-95 l3_cache_access_sf_tag register bit assignments

Bits Name Access Reset value Function
[63:44] - RAZ/WI 0x0 Reserved
[43:0] l3_cache_access_sf_tag RO 0x0 SF tag debug read data register

Error Syndrome 0 register, L3 cache

The err_syndrome_reg0 register is at offset 0x0400. Its characteristics are:

PurposeIndicates bit errors in the L3 cache.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the err_syndrome_reg0 register bit assignments.

Figure 3-82 err_syndrome_reg0 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the err_syndrome_reg0 register bit assignments.

Table 3-96 err_syndrome_reg0 register bit assignments

Bits Name Access Reset value Function
[63] err_exntd RO 0 Error extended.
[62] first_err_vld RO 0 First error valid.
[61:60] err_class RO 0x0 Error classification.
[59] mult_err RO 0 Multiple errors.
[58:43] err_count RO 0x0 Corrected error count.
[42:20] - RAZ/WI 0x0 Reserved
[19:8] err_count_set RO 0x0 HN-F single-bit ECC error count set address.
[7] err_count_ovrflw RO 0 HN-F single-bit error counter overflow.
[6] err_count_match RO 0 HN-F single-bit ECC error count applies to same type and set.
[5:4] err_count_type RO 0b00

HN-F single-bit ECC counter type:

0b00L3 data single-bit count.
0b01L3 tag single-bit count.
0b10SF tag single-bit count.
[3] par_err_id RO 0 Byte parity error.
[2:0] err_id RO 0b000

HN-F error syndrome register error type:

0b100L3 data double-bit ECC error.
0b101L3 tag double-bit ECC error.
0b110SF tag double-bit ECC error.
0b111CHI bus slave error.

Error Syndrome 1 register, L3 cache

The err_syndrome_reg1 register is at offset 0x0408. Its characteristics are:

PurposeIndicates the address of the first tag error.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the err_syndrome_reg1 register bit assignments.

Figure 3-83 err_syndrome_reg1 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the err_syndrome_reg1 register bit assignments.

Table 3-97 err_syndrome_reg1 register bit assignments

Bits Name Access Reset value Function
[63:55] Reserved RAZ/WI 0x0 -
[54:48] err_srcid RO 0b0000000 HN-F error syndrome SrcID[6:0] for byte parity errors only
[47:46] Reserved RAZ/WI 0b00 -
[45:44] err_optype RO 0b00

HN-F error syndrome OpType[1:0] for byte parity errors only

0b00WRUNIQ or WRLUNIQ.
0b01WRBACKPTL.
0b10WRNOSNP or WRNOSNPFULL.
0b11All others.
[43:0] err_addr RO 0x0 HN-F error syndrome address for double-bit ECC or byte parity errors only

L3 cache Error Syndrome Clear register

The err_syndrome_clr register is at offset 0x0480. Its characteristics are:

PurposeClears the error log in the Error Syndrome 0 register.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the err_syndrome_clr register bit assignments.

Figure 3-84 err_syndrome_clr register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the err_syndrome_clr register bit assignments.

Table 3-98 err_syndrome_clr register bit assignments

Bits Name Access Reset value Function
[63] - RAZ/WI 0 Reserved
[62] first_err_vld_clr WO 0 Clears the first_err_vld bit in the Error Syndrome 0 register
[61:60] - RAZ/WI 0b00 Reserved
[59] mult_err_clr WO 0 Clears the mult_err bit in the Error Syndrome 0 register
[58:0] - RAZ/WI 0x0 Reserved

HN-F Auxiliary Control register

The hnf_aux_ctl register is at offset 0x0500. Its characteristics are:

PurposeControls various modes of HN-F operation.
Usage constraintsThis register can be modified only with prior written permission from ARM.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the hnf_aux_ctl register bit assignments.

Figure 3-85 hnf_aux_ctl register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the hnf_aux_ctl register bit assignments.

Table 3-99 hnf_aux_ctl register bit assignments

Bits Name Access Reset value Function
[63:14] - RAZ/WI 0x0 Reserved
[13] hnf_ocm_allways_en RW 0 All L3 way OCM support enable.
[12] hnf_ocm_en RW 0 Region lock with OCM support enable.
[11] hnf_honor_ewa RW 0

This bit controls whether the HN-F honors the state of the Early Write Acknowledge (EWA) bit within the MemAttr field of a REQ flit:

0 = The HN-F ignores the state of the EWA bit. Therefore, the HN-F can send a write completion response before it receives completion from the SN.

1 = The HN-F honors the state of the EWA bit. If EWA = 0, then the HN-F only sends Completion when it receives a completion from the SN.

[10:8] - RAZ/WI 0b000 Reserved
[7] dis_qos_pcrdtype RW 0 Disable QoS based PCrdType assignment.
[6] dis_snp_once RW Value depends on customer configuration Disable SnpOnce. SnpOnce is converted to SnpShared.
[5] l3_no_alloc RW 0 Disable L3 allocation for Non-shareable Cacheable transactions.
[4] rd_once_no_alloc RW 0 Disable ReadOnce allocation in the L3 from RN-Is.
[3] rev_qos_pool_alloc RW 0 Reverse QoS pool allocation algorithm.
[2] no_wu_alloc RW 0 Disable WriteUnique and WriteLineUnique allocations in L3.
[1] - RAZ/WI 0 Reserved
[0] hnf_only_mode RW 0 HN-F-only mode with no L3 and snoop filter.

PMU Event Select register, L3 cache

The pmu_event_sel register is at offset 0x0600. Its characteristics are:

PurposeSelects the PMU events to be counted.
Usage constraintsBefore any field in this register can be selected for transmission by the debug and test control logic in the XP, that field must be set to a valid value other than 0x0.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the pmu_event_sel register bit assignments.

Figure 3-86 pmu_event_sel register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the pmu_event_sel register bit assignments.

Table 3-100 pmu_event_sel register bit assignments

Bits Name Access Reset value Function
[63:16] - RAZ/WI 0x0 Reserved
[15:12] pmu_event3_id RW 0x0

PMU Event 3 ID. The event is specified as a 4-bit ID with the following encodings:

0b0000Null (no event).
0b0001PMU_HN_CACHE_MISS_EVENT. Counts the total cache misses. This is the first time lookup result, and is high priority.
0b0010PMU_HNL3_SF_CACHE_ACCESS_EVENT. Counts the number of cache accesses. This is the first time access, and is high priority.
0b0011PMU_HN_CACHE_FILL_EVENT. Counts the total allocations in the HN L3 cache, and all cache line allocations to the L3 cache.
0b0100PMU_HN_POCQ_RETRY_EVENT. Counts the number of requests that have been retried.
0b0101PMU_HN_POCQ_REQS_RECVD_EVENT. Counts the number of requests received by HN.
0b0110PMU_HN_SF_HIT_EVENT. Counts the number of snoop filter hits.
0b0111PMU_HN_SF_EVICTIONS_EVENT. Counts the number of snoop filter evictions. Cache invalidations are initiated.
0b1000PMU_HN_SNOOPS_SENT_EVENT. Counts the number of snoops sent. Does not differentiate between broadcast or directed snoops.
0b1001PMU_HN_SNOOPS_BROADCAST_EVENT. Counts the number of snoop broadcasts sent.
0b1010PMU_HN_L3_EVICTION_EVENT. Counts the number of L3 evictions.
0b1011PMU_HN_L3_FILL_INVALID_WAY_EVENT. Counts the number of L3 fills to an invalid way.
0b1100PMU_HN_MC_RETRIES_EVENT. Counts the number of transactions retried by the memory controller.
0b1101PMU_HN_MC_REQS_EVENT. Counts the number of requests to the memory controller.
0b1110PMU_HN_QOS_HH_RETRY_EVENT. Counts the number of times a highest-priority QoS class was retried at the HN-F.

All other values are Reserved.

[11:8] pmu_event2_id RW 0x0

PMU Event 2 ID.

See pmu_event3_id in this table for more information.

[7:4] pmu_event1_id RW 0x0

PMU Event 1 ID.

See pmu_event3_id in this table for more information.

[3:0] pmu_event0_id RW 0x0

PMU Event 0 ID.

See pmu_event3_id in this table for more information.

HN-F Identification register

The oly_hnf_oly_id register is at offset 0xFF00. Its characteristics are:

PurposeContains the component identification information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-6 HN-F register summary.

The following figure shows the oly_hnf_oly_id register bit assignments.

Figure 3-87 oly_hnf_oly_id register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the oly_hnf_oly_id register bit assignments.

Table 3-101 oly_hnf_oly_id register bit assignments

Bits Name Access Reset value Function
[63:15] - RAZ/WI 0x0 Reserved
[14:8] node_id RO Value is specific to each HN-F The node ID of the HN-F
[7:5] - RAZ/WI 0b000 Reserved
[4:0] oly_id RO 0x4 Indicates that this node is an HN-F
Non-ConfidentialPDF file icon PDF versionARM 100052_0001_00_en
Copyright © 2014, 2015, 2017 ARM Limited or its affiliates. All rights reserved.