2.9.3 Error handling requirements

The CCN-502 follows the CHI error handling methodology.

This section describes the specific behavior of the CCN-502.

Error reporting rules

The rules regarding error reporting in the CCN-502 are:

  • Any error originating in the CCN-502 is reported.
  • Any error originating outside the CCN-502 but corrupting the CCN-502 is reported.
  • The HN-I can report an error in a response packet from outside the CCN-502 if it does not propagate the response any further, as controlled by the HN-I PoS Control register.
  • All non-write errors, reported or otherwise, are propagated where possible.
  • All non-posted write errors are propagated where possible.

Suggested interrupt handling flow

This section describes the suggested interrupt handling flow using the CCN-502 registers.

At the device

Complete the following steps to handle interrupts at the device.

Procedure

  1. When an error occurs, and the first_err_vld bit is not asserted:
    1. Log the error information in the applicable Error Syndrome register and set the first_err_vld bit. The information to be logged is device-specific.
    2. Signal the error to the MN using the error signal bus.
  2. If the first_err_vld bit is already asserted and the mult_err bit is not set, then set the mult_err bit.
  3. If it is set, do nothing. You can set the mult_err bit multiple times, and ignore this step.
At the MN

The MN sets the INTREQ signal HIGH under certain conditions.

The conditions are:

  • At least one bit in the applicable Error Type Valid register is set.
  • The corresponding data_int_status, to mask the type of register, is not asserted in the Error Interrupt Status register.
For the error handling software on detection of assertion of INTREQ

Complete the following steps to handle errors on detection of INTREQ.

Procedure

  1. Read the three Error Signal Valid registers.
    Error Signal valid registers are atomically cleared on a read.
  2. Read the six Error Type registers.
  3. For each device x that has its err_sig_val_x bits set, read the applicable Error Syndrome 0 register, except in the case of an error signaled by XP-0. If the error is signaled by XP-0, read the Error Syndrome registers of all XPs to determine which particular XP detected the parity error.
    Depending on the error device type, the error handler might not have to read any of the other Error Syndrome registers.
  4. When the error handler has read all the required Error Syndrome registers:
    1. In the applicable Error Signal Valid register, write the following to each device x that has its err_sig_val_x bits set. If the error is signaled by XP-0, repeat the following write to either each XP that has its first_err_vld bit set or to all XPs. More than one XP might have detected errors.
    2. To the Error Syndrome Clear register, write 1 to bits[62,59]. Ignore the remaining bits.
      An example of data to be written for 64-bit and 32-bit registers is:
      • A 64-bit write of 0x4800000000000000 or 0xFFFFFFFFFFFFFFFF to 0x480.
      • A 32-bit write of 0x48000000 or 0xFFFFFFFF to 0x484.
      This clears the first_err_vld and mult_err bits.
  5. Write to the Error Interrupt Status register to deassert the interrupt.
    Setting bit[0] = 1 enables writes to bit[4], and setting bit[4] = 1 disables the INTREQ interrupt. An example of data to be written for 64-bit and 32-bit registers is:
    • A 64-bit write of 0x0000000000000011.
    • A 32-bit write of 0x00000011.
  6. Optional: Write to the global interrupt controller to enable a new interrupt capture.
  7. Optional: Write to the Error Interrupt Status register to enable the interrupt.
    Setting bit[0] = 1 enables writes to bit[4], and setting bit[4] = 0 enables the INTREQ interrupt. An example of data to be written for 64-bit and 32-bit registers is:
    • A 64-bit write of 0x0000000000000001.
    • A 32-bit write of 0x00000001.

Error Interrupt Status register values

This section suggests values that you can write to the register depending on the state of the CCN-502.

The following table lists the values to write to the Error Interrupt Status register for various scenarios.

Table 2-3 Error Interrupt Status register values

Scenario Value
To disable interrupt generation because of a PMU event overflow. 0x88
To disable interrupt generation because of corrected errors. 0x44
To disable interrupt generation because of any error. 0x22
To deassert an asserted INTREQ signal. This is not a sticky bit, that is, it always reads as zero. 0x11

Error reporting and signaling at the HN-I

Errors are reported at the HN-I for a number of different reasons.

The HN-I signals an error to the MN if any of the following conditions apply:

  • It receives a Cacheable read, Cacheable write, or a Cache maintenance Operation CMO, or, it receives an MN-bound configuration read or write that does not meet the requirements specified in 3.1.3 Requirements of configuration register reads and writes. These requests are steered to the HN-I. Signaling of errors to the MN can be enabled and disabled by using bit[2] (err_req_en) of the sa_aux_ctl register. By default this bit is set.
  • It receives an error response on BRESP from downstream. This can be enabled and disabled by using bit[3] (err_rsp_en) of the sa_aux_ctl register. By default this bit is clear.

The HN-I sends a Non-data Error (NDERR) response to a requesting RN if any of the following applies:

  • It receives an HN-I or MN-bound coherent read request.
  • It receives an HN-I or MN-bound CMO, and bit[8] (rsperr_cmo_en) of the sa_aux_ctl register is set. By default this bit is clear.

Data Errors (DERR) or NDERRs from downstream read responses are passed on unmodified to the requesting RN.

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