3.3.4 HN-I register descriptions

This section lists the HN-I registers.

PoS Control register

The pos_control register is at offset 0x0000. Its characteristics are:

PurposeSelects Point-of-Serialization (PoS) related features.
Usage constraintsBefore writing this register, ensure that all previous transactions to the HN-I have completed, and then you must issue and wait for completion of a DSB or ECBarrier.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-7 HN-I register summary.

The following figure shows the pos_control register bit assignments.

Figure 3-88 pos_control register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the pos_control register bit assignments.

Table 3-102 pos_control register bit assignments

Bits Name Access Reset value Function
[63:4] - RAZ/WI 0x0 Reserved.
[3] awcache0_ovrd_val RW 0 If bit[1] of this register is set, AWCACHE[0] is driven from this bit.
[2] arcache0_ovrd_val RW 0 If bit[1] of this register is set, ARCACHE[0] is driven from this bit.
[1] axcache_override RW 0 Set to 1 to override AWCACHE[0] and ARCACHE[0] on the AMBA interface.
[0] hni_pos_en RW 1

Indicates status of HN-I PoS:

1HN-I is final PoS.
0HN-I is not final PoS. See the pos_* control bits in the sa_aux_ctl register. Violates the CHI GO definition when the hni_pos_en bit is 0.

PCIeRC RN-I Node ID List register

The pcierc_rni_nodeid_list register is at offset 0x008. Its characteristics are:

PurposeA bit vector showing the list of all RN-Is with PCIe RC connected in the system.
Usage constraintsCan be read from in ALL states. Cannot be changed.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-7 HN-I register summary.

The following figure shows the bit assignments.

Figure 3-89 pcierc_rni_nodeid_list register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-103 pcierc_rni_nodeid_list Register bit assignments

Bits Name Access Reset value Function
[63:0] pcierc_rni_nodeid_list RW 0x0 A bit vector showing the list of all RN-Is with PCIe RC connected in the system.

Error Syndrome 0 register, HN-I

The err_syndrome_reg0 register is at offset 0x0400. Its characteristics are:

PurposeIndicates the HN-I error log information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-7 HN-I register summary.

The following figure shows the err_syndrome_reg0 register bit assignments.

Figure 3-90 err_syndrome_reg0 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the err_syndrome_reg0 register bit assignments.

Table 3-104 err_syndrome_reg0 register bit assignments

Bits Name Access Reset value Function
[63] err_exntd RO 0 Error extended.
[62] first_err_vld RO 0 First error valid.
[61:60] err_class RO 0x0 Error classification.
[59] mult_err RO 0 Multiple errors.
[58:43] corrected_err_count RO 0x0 Corrected error count.
[42:0] component_specific_reg0 RO 0x0

Component-specific error information:

Bits[42:4]

Error log 1:

[42]Reserved.
[41:40]PCrdType.
[39:37]SIZE.
[36:35]SnpAttr.
[34:31]MemAttr.
[30:29]ORDER.
[28]NS.
[27]DYNPCRD.
[26:16]TXNIDa.
[18:16]LPID.
[15:9]SRCIDa.
[8:4]OPCODE.
Bits[3:0]

Error type:

0b0001Unsupported opcode (CMO/CU/MU).
0b0010Cacheable read request.
0b0011Cacheable write request.
0b0100Downstream write response error.
0b0101MN read request.
0b0110MN write request.
0b0101MN unsupported opcode (CMO/CU/MU).

All other values are Reserved.

Error Syndrome 1 register, HN-I

The err_syndrome_reg1 register is at offset 0x0408. Its characteristics are:

PurposeIndicates the HN-I error log information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-7 HN-I register summary.

The following figure shows the err_syndrome_reg1 register bit assignments.

Figure 3-91 err_syndrome_reg1 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the err_syndrome_reg1 register bit assignments.

Table 3-105 err_syndrome_reg1 register bit assignments

Bits Name Access Reset value Function
[63:0] component_specific_reg1 RO 0x0

Component-specific error information extended:

Error Log2[43:0] = Address[43:0].

Error Log2[63:44] = Reserved.

HN-I Error Syndrome Clear register

The err_syndrome_clr register is at offset 0x0480. Its characteristics are:

PurposeClears the error log in the Error Syndrome 0 register.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-7 HN-I register summary.

The following figure shows the err_syndrome_clr register bit assignments.

Figure 3-92 err_syndrome_clr register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the err_syndrome_clr register bit assignments.

Table 3-106 err_syndrome_clr register bit assignments

Bits Name Access Reset value Function
[63] - RAZ/WI 0 Reserved
[62] first_err_vld_clr WO 0 Clears the first_err_vld bit in the Error Syndrome 0 register
[61:60] - RAZ/WI 0b00 Reserved
[59] mult_err_clr WO 0 Clears the mult_err bit in the Error Syndrome 0 register
[58:0] - RAZ/WI 0x0 Reserved

SA Auxiliary Control register, HN-I

The sa_aux_ctl register is at offset 0x0500. Its characteristics are:

PurposeAuxiliary control of the HN-I.
Usage constraintsThis register can be modified only with prior written permission from ARM.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-7 HN-I register summary.

The following figure shows the sa_aux_ctl register bit assignments.

Figure 3-93 sa_aux_ctl register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the sa_aux_ctl register bit assignments.

Table 3-107 sa_aux_ctl register bit assignments

Bits Name Access Reset value Function
[63:12] - RAZ/WI 0x0 Reserved
[11] honor_ewa_en RW 0 Propagate BRESP to the requesting RN, for non-posted writes.
[10] - WI 1 Reserved
[9] ser_devne_wr RW 0 Serialize Device-nGnRnE writes.
[8] rsperr_cmo_en RW 0 Enable sending Non-data Error (NDERR) response on CMO. Applies to all requests with Comp-only response semantics.
[7] pos_early_eobarrsp_en RW 1

Enable sending early completion response for EOBarrier from HN-I. Used to improve EOBarrier performance.

Violates the CHI GO definition when the hni_pos_en bit in the pos_control register is 0.

[6] pos_early_rdack_en RW 1

Enable sending early read receipts from HN-I. Used to improve ordered read performance.

Violates the CHI GO definition when the hni_pos_en bit in the pos_control register is 0.

[5] pos_early_wr_comp_en RW 1

Enable early write completions for all writes that allow early acknowledgment. Used to improve write performance.

Violates the CHI GO definition when the hni_pos_en bit in the pos_control register is 0.

[4] pos_terminate_barriers RW 1 Enable termination of barriers before AMBA interface. Used when no downstream barrier capability exists (AXI4) or is required.
[3] err_rsp_en RW 0 Set to 1, to enable signaling an error to the MN on response.
[2] err_req_en RW 1 Set to 1, to enable signaling an error to the MN on request.
[1] qos_schedule_en RW 1 Set to 1, to enable QoS based scheduling of the AMBA requests.
[0] rdreq_byp_en RW 1 Set to 1, to enable read bypass path.

HN-I Identification register

The oly_hni_oly_id register is at offset 0xFF00. Its characteristics are:

PurposeContains the component identification information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-7 HN-I register summary.

The following figure shows the oly_hni_oly_id register bit assignments.

Figure 3-94 oly_hni_oly_id register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the oly_hni_oly_id register bit assignments.

Table 3-108 oly_hni_oly_id register bit assignments

Bits Name Access Reset value Function
[63:15] - RAZ/WI 0x0 Reserved
[14:8] node_id RO 0x0 The node ID of the HN-I
[7:5] - RAZ/WI 0b000 Reserved
[4:0] oly_id RO 0x5 Indicates that this node is an HN-I
a These fields are logged for downstream write response errors.
Non-ConfidentialPDF file icon PDF versionARM 100052_0001_00_en
Copyright © 2014, 2015, 2017 ARM Limited or its affiliates. All rights reserved.