2.12.4 HN-F SAM

The HN-F SAM is similar to the RN SAM. It is present in all HN-F partitions to route transactions to the SN-Fs, which are generally memory controllers. The HN-F has mechanisms to identify RNs for snoops that are not part of the HN-F SAM and so are not described in this section. The following figure shows the HN-F SAM.

Figure 2-7 HN-F SAM
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The HN-F SAM supports one, two, three, or four SN-Fs. To determine the particular SN-F for a particular address, you must use a hash function. The hash function depends on:

The following table shows the function that generates the SN-F TgtID and the address bits that must be used by the SN-F to guarantee contiguity of addresses presented to the SN-F. ARM recommends that the SoC designer carefully analyze the address mapping functions between the request source and MC to understand the resulting address map for each MC. SN-F and HN-F identifiers refer to NodeIDs.


The CCN-502 does not modify the address sent to the SN-F. The system designer is responsible for ensuring that the appropriate address bits are used within the memory subsystem to enable security, contiguity of memory regions, and other issues as required.

Table 2-5 HN-F SAM map

HN-Fs SN-Fs SN-Fs at (NodeID) HN-F partitions Which SN-F? (NodeID) SN-F address
2 2 2 and 8 3 and 9 2 and 8 {Address[43:9], Address[7:0]}
4 2 2 and 10 3, 5 2 {Address[43:8], Address[6:0]}
11, 13 10
4 and 12 3, 5 4
11, 13 12
3 - - Use 3 SN striping Use 3 SN striping
4 2, 4, 10, 12 3 2 {Address[43:9], Address[6:0]}
5 4
11 10
13 12

3 SN-F memory striping

In the 3 SN-F hashed mode, addresses are striped at 256-byte granularity between the 3 SN-Fs.

Each HN-F uses the hn_cfg_three_sn_en bit in its hnf_sam_control register to enable routing to 3 SNs.

In the hnf_sam_control register, the hn_cfg_sam_top_address_bit0 and hn_cfg_sam_top_address_bit1 fields must be configured at boot time. These fields must be set to the top address bits of addressable DRAM. These two address bits are decoded, and are then used with a hashing function to determine the target SN-F. For example, if 3GB of DRAM are used, that is, 1GB at each SN, then the hn_cfg_sam_top_address_bit1 field must be set to 31, and the hn_cfg_sam_top_address_bit0 field must be set to 30.


Memory aliasing or holes can occur if the top two address bits cannot be used to decode between the three DRAM regions.

The full physical address is sent to the SNs, but the memory controller must ignore the top 2 bits of the addressable DRAM. Continuing the example of 3GB, the memory controller must ignore bits[31:30] of the address, using only bits[29:0].

Each HN-F uses the hn_cfg_sn<N>_nodeid fields, in its hnf_sam_control register, to map each target index to a slave node. For example, if the target index is:

  • 0, the hn_cfg_sn0_nodeid field defines the target SN.
  • 1, the hn_cfg_sn1_nodeid field defines the target SN.
  • 2, the hn_cfg_sn2_nodeid field defines the target SN.

If the CCN-502 is configured at build time to have three SNs, then the default values are shown in the following table.

Table 2-6 3 SN striping values

Chosen SNs SN 0 SN 1 SN 2
2, 4, and 10 2 4 10
4, 10, and 12 4 10 12
10, 12, and 2 2 10 12
12, 2, and 4 2 4 12
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