3.3.2 XP register descriptions

This section lists the XP registers.

XP Routing Control register

The xp_routing_control register is at offset 0x0000. Its characteristics are:

PurposeControls the XP routing.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the xp_routing_control register bit assignments.

Figure 3-30 xp_routing_control register bit assignments
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The following table shows the xp_routing_control register bit assignments.

Table 3-40 xp_routing_control register bit assignments

Bits Name Access Reset value Function
[63:8] - RAZ/WI 0x0 Reserved
[7:2] - RW 0x0 Reserved
[1] dev1_nsm_rout_ovr RW 0 Device 1 port non-broadcast routing vector override enable
[0] dev0_nsm_rout_ovr RW 0 Device 0 port non-broadcast routing vector override enable

XP Device 0 Port NSM Routing register

The dev0_nsm_routing_vector register is at offset 0x0008. Its characteristics are:

PurposeSpecifies the NSM routing information for an XP device 0 port.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev0_nsm_routing_vector register bit assignments.

Figure 3-31 dev0_nsm_routing_vector register bit assignments
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The following table shows the dev0_nsm_routing_vector register bit assignments.

Table 3-41 dev0_nsm_routing_vector register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] dev0_nsm_rout_vec RW 0x0 Device 0 non-broadcast routing vector

XP Device 1 Port NSM Routing register

The dev1_nsm_routing_vector register is at offset 0x0010. Its characteristics are:

PurposeSpecifies the NSM routing information for an XP device 1 port.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev1_nsm_routing_vector register bit assignments.

Figure 3-32 dev1_nsm_routing_vector register bit assignments
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The following table shows the dev1_nsm_routing_vector register bit assignments.

Table 3-42 dev1_nsm_routing_vector register bit assignments

Bits Name Access Reset value Function
[63:16] - RAZ/WI 0x0 Reserved
[15:0] dev1_nsm_rout_vec RW 0x0 Device 1 non-broadcast routing vector

Device 0 Port QoS Control register

The dev0_qos_control register is at offset 0x0110. Its characteristics are:

PurposeControls the QoS settings for the device 0 port.
Usage constraintsBefore writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev0_qos_control register bit assignments.

Figure 3-33 dev0_qos_control register bit assignments
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The following table shows the dev0_qos_control register bit assignments.

Table 3-43 dev0_qos_control register bit assignments

Bits Name Access Reset value Function
[63:20] - RAZ/WI 0x0 Reserved
[19:16] dev0_qos_override RW 0x0 Port 0 QoS override value.
[15:7] - RAZ/WI 0x0 Reserved
[6] dev0_pqv_mode RW 0

Configures the mode of the QoS regulator during period mode for bandwidth regulation:

0Normal mode. The QoS value is stable when the master is idle.
1Quiesce high mode. The QoS value tends to the maximum value when the master is idle.
[5] - RAZ/WI 0 Reserved
[4] dev0_reg_mode RW 0

Configures the mode of the QoS regulator:

0Latency mode.
1Period mode, for bandwidth regulation.
[3] - RAZ/WI 0 Reserved
[2] dev0_qos_override_en RW 0 Port 0 QoS override enable. When set, this bit enables the QoS value on inbound transactions to be overridden. When this device port is connected to a protocol bridge, this bit must be set to 0.
[1] - RAZ/WI 0 Reserved
[0] dev0_lat_en RW 0 Port 0 QoS regulation enable. When set, this bit enables regulation.

Device 0 Port QoS Latency Target register

The dev0_qos_lat_tgt register is at offset 0x0118. Its characteristics are:

PurposeControls the QoS target latency, in cycles, for the regulation of the device 0 port. A value of 0 corresponds to no regulation.
Usage constraintsBefore writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev0_qos_lat_tgt register bit assignments.

Figure 3-34 dev0_qos_lat_tgt register bit assignments
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The following table shows the dev0_qos_lat_tgt register bit assignments.

Table 3-44 dev0_qos_lat_tgt register bit assignments

Bits Name Access Reset value Function
[63:12] - RAZ/WI 0x0 Reserved
[11:0] dev0_lat_tgt RW 0x0 Port 0 target latency

Device 0 Port QoS Latency Scale register

The dev0_qos_lat_scale register is at offset 0x0120. Its characteristics are:

PurposeControls the QoS target latency scale factor for the device 0 port. It is coded for powers of 2 in the range 2–5 to 2–12.
Usage constraintsBefore writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev0_qos_lat_scale register bit assignments.

Figure 3-35 dev0_qos_lat_scale register bit assignments
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The following table shows the dev0_qos_lat_scale register bit assignments.

Table 3-45 dev0_qos_lat_scale register bit assignments

Bits Name Access Reset value Function
[63:3] - RAZ/WI 0x0 Reserved
[2:0] dev0_lat_scale RW 0x0 Port 0 QoS scale factor, in powers of 2 in the range 2–5 to 2–12

Device 0 Port QoS Latency Range register

The dev0_qos_lat_range register is at offset 0x0128. Its characteristics are:

PurposeControls the QoS minimum and maximum values generated by the QoS latency regulator for the device 0 port.
Usage constraintsBefore writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev0_qos_lat_range register bit assignments.

Figure 3-36 dev0_qos_lat_range register bit assignments
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The following table shows the dev0_qos_lat_range register bit assignments.

Table 3-46 dev0_qos_lat_range register bit assignments

Bits Name Access Reset value Function
[63:12] - RAZ/WI 0x0 Reserved
[11:8] dev0_lat_max_qos RW 0x0 Port 0 QoS maximum value
[7:4] - RAZ/WI 0x0 Reserved
[3:0] dev0_lat_min_qos RW 0x0 Port 0 QoS minimum value

Device 1 Port QoS Control register

The dev1_qos_control register is at offset 0x0210. Its characteristics are:

PurposeControls the QoS settings for the device 1 port.
Usage constraintsBefore writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev1_qos_control register bit assignments.

Figure 3-37 dev1_qos_control register bit assignments
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The following table shows the dev1_qos_control register bit assignments.

Table 3-47 dev1_qos_control register bit assignments

Bits Name Access Reset value Function
[63:20] - RAZ/WI 0x0 Reserved
[19:16] dev1_qos_override RW 0x0 Port 1 QoS override value.
[15:7] - RAZ/WI 0x0 Reserved
[6] dev1_pqv_mode   0

Configures the mode of the QoS regulator during period mode for bandwidth regulation:

0Normal mode. The QoS value is stable when the master is idle.
1Quiesce high mode. The QoS value tends to the maximum value when the master is idle.
[5] - RAZ/WI 0 Reserved
[4] dev1_reg_mode   0

Configures the mode of the QoS regulator:

0Latency mode.
1Period mode, for bandwidth regulation.
[3] - RAZ/WI 0 Reserved
[2] dev1_qos_override_en RW 0 Port 1 QoS override enable. When set, this bit enables the QoS value on inbound transactions to be overridden. When this device port is connected to a protocol bridge, this bit must be set to 0.
[1] - RAZ/WI 0 Reserved
[0] dev1_lat_en RW 0 Port 1 QoS regulation enable. When set, this bit enables regulation.

Device 1 Port QoS Target Latency register

The dev1_qos_lat_tgt register is at offset 0x0218. Its characteristics are:

PurposeControls the QoS target latency, in cycles, for the regulation of the device 1 port. A value of 0 corresponds to no regulation.
Usage constraintsBefore writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev1_qos_lat_tgt register bit assignments.

Figure 3-38 dev1_qos_lat_tgt register bit assignments
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The following table shows the dev1_qos_lat_tgt register bit assignments.

Table 3-48 dev1_qos_lat_tgt register bit assignments

Bits Name Access Reset value Function
[63:12] - RAZ/WI 0x0 Reserved
[11:0] dev1_lat_tgt RW 0x0 Port 1 target latency

Device 1 Port QoS Latency Scale register

The dev1_qos_lat_scale register is at offset 0x0220. Its characteristics are:

PurposeControls the QoS target latency scale factor for the device 1 port. It is coded for powers of 2 in the range 2–5 to 2–12.
Usage constraintsBefore writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev1_qos_lat_scale register bit assignments.

Figure 3-39 dev1_qos_lat_scale register bit assignments
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The following table shows the dev1_qos_lat_scale register bit assignments.

Table 3-49 dev1_qos_lat_scale register bit assignments

Bits Name Access Reset value Function
[63:3] - RAZ/WI 0x0 Reserved
[2:0] dev1_lat_scale RW 0x0 Port 1 QoS scale factor, in powers of 2 in the range 2–5 to 2–12

Device 1 Port QoS Latency Range register

The dev1_qos_lat_range register is at offset 0x0228. Its characteristics are:

PurposeControls the QoS minimum and maximum values generated by the QoS latency regulator for the device 1 port.
Usage constraintsBefore writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dev1_qos_lat_range register bit assignments.

Figure 3-40 dev1_qos_lat_range register bit assignments
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The following table shows the dev1_qos_lat_range register bit assignments.

Table 3-50 dev1_qos_lat_range register bit assignments

Bits Name Access Reset value Function
[63:12] - RAZ/WI 0x0 Reserved
[11:8] dev1_lat_max_qos RW 0x0 Port 1 QoS maximum value
[7:4] - RAZ/WI 0x0 Reserved
[3:0] dev1_lat_min_qos RW 0x0 Port 1 QoS minimum value

Debug and Trace Configuration register

The dt_config register is at offset 0x0300. Its characteristics are:

PurposeConfigures the debug and trace logic.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_config register bit assignments.

Figure 3-41 dt_config register bit assignments
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The following table shows the dt_config register bit assignments.

Table 3-51 dt_config register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:28] dt_cfg_7 RW 0x0 Select source to be transmitted on DTBus[7]a
[27:24] dt_cfg_6 RW 0x0 Select source to be transmitted on DTBus[6]a
[23:20] dt_cfg_5 RW 0x0 Select source to be transmitted on DTBus[5]a
[19:16] dt_cfg_4 RW 0x0 Select source to be transmitted on DTBus[4]a
[15:12] dt_cfg_3 RW 0x0 Select source to be transmitted on DTBus[3]a
[11:8] dt_cfg_2 RW 0x0 Select source to be transmitted on DTBus[2]a
[7:4] dt_cfg_1 RW 0x0 Select source to be transmitted on DTBus[1]a
[3:0] dt_cfg_0 RW 0x0 Select source to be transmitted on DTBus[0]a

Table 3-52 dt_cfg field values

Value Description
0x0 DT bus input from previous XP (pass-through)
0x1 OR of watchpoint 0 and 1
0x2 Watchpoint 0
0x3 Watchpoint 1
0x4 XP PMU event 0
0x5 XP PMU event 1
0x6 XP PMU event 2
0x7 XP PMU event 3
0x8 Device 0 PMU event 0
0x9 Device 0 PMU event 1
0xA Device 0 PMU event 2
0xB Device 0 PMU event 3
0xC Device 1 PMU event 0
0xD Device 1 PMU event 1
0xE Device 1 PMU event 2
0xF Device 1 PMU event 3

Debug and Trace Interface Select register

The dt_interface_sel register is at offset 0x0308. Its characteristics are:

PurposeSelects the interface to watch during debug.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_interface_sel register bit assignments.

Figure 3-42 dt_interface_sel register bit assignments
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The following table shows the dt_interface_sel register bit assignments.

Table 3-53 dt_interface_sel register bit assignments

Bits Name Access Reset value Function
[63:13] - RAZ/WI 0x0 Reserved
[12:10] dt_vc_sel1 RW 0b000

Selection of channel type:

0b000Select REQ channel.
0b001Select RESP channel.
0b010Select SNP channel.
0b011Select DATA channel.
0b100Reserved.
0b101Reserved.
0b110Reserved.
0b111Select DATB channel.
[9] dt_dev_sel1 RW 0

Selection of device 0 or device 1 port in specified XP:

0Select device port 0.
1Select device port 1.
[8] dt_io_sel1 RW 0

Selection of TX or RX type for specified channel:

0Select RX channel.
1Select TX channel.
[7:5] - RAZ/WI 0x0 Reserved
[4:2] dt_vc_sel0 RW 0b000

Selection of channel type:

0b000Select REQ channel.
0b001Select RESP channel.
0b010Select SNP channel.
0b011Select DATA channel.
0b100Reserved.
0b101Reserved.
0b110Reserved.
0b111Select DATB channel.
[1] dt_dev_sel0 RW 0

Selection of device 0 or device 1 port in specified XP:

0Select device port 0.
1Select device port 1.
[0] dt_io_sel0 RW 0

Selection of TX or RX type for specified channel:

0Select RX channel.
1Select TX channel.

Debug and Trace Comparison Low Value 0 register

The dt_cmp_val0_l register is at offset 0x0310. Its characteristics are:

PurposeValue used for least-significant bits of watchpoint comparison.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_cmp_val0_l register bit assignments.

Figure 3-43 dt_cmp_val0_l register bit assignments
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The following table shows the dt_cmp_val0_l register bit assignments.

Table 3-54 dt_cmp_val0_l register bit assignments

Bits Name Access Reset value Function
[63] - RAZ/WI 0x0 Reserved
[62:0] dt_cmp_val0_l RW 0x0

Flit mapping:

val/mask[43:0]ADDR
val/mask[45:44]CCID
val/mask[47:46]DATAID
val/mask[55:48]DBID
val/mask[56:56]DYNPCRD
val/mask[57:57]EXCL
val/mask[58:58]EXPCOMPACK
val/mask[59:59]LIKELYSHARED
val/mask[62:60]LPID

Debug and Trace Comparison High Value 0 register

The dt_cmp_val0_h register is at offset 0x0318. Its characteristics are:

PurposeValue used for most-significant bits of watchpoint comparison.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_cmp_val0_h register bit assignments.

Figure 3-44 dt_cmp_val0_h register bit assignments
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The following table shows the dt_cmp_val0_h register bit assignments.

Table 3-55 dt_cmp_val0_h register bit assignments

Bits Name Access Reset value Function
[63:60] - RAZ/WI 0x0 Reserved
[59:0] dt_cmp_val0_h RW 0x0

Flit mapping:

val/mask[3:0]MEMATTR
val/mask[4:4]MEMATTR_ALLOCATE
val/mask[5:5]MEMATTR_CACHEABLE
val/mask[6:6]MEMATTR_DEVICE
val/mask[7:7]MEMATTR_EARLYWRACK
val/mask[8:8]NS
val/mask[13:9]OPCODE
val/mask[15:14]ORDER
val/mask[17:16]PCRDTYPE
val/mask[21:18]QOS
val/mask[24:22]RESP
val/mask[26:25]RESPERR
val/mask[30:27]RSVDC
val/mask[33:31]SIZE
val/mask[35:34]SNPATTR
val/mask[36:36]SNPATTR_SNOOPABLE
val/mask[37:37]SNPATTR_SNPDOMAIN
val/mask[44:38]SRCID
val/mask[51:45]TGTID
val/mask[59:52]TXNID

Debug and Trace Comparison Low Mask 0 register

The dt_cmp_mask0_l register is at offset 0x0320. Its characteristics are:

Purpose

Mask used for qualification of least-significant bits of watchpoint comparison:

0b0The corresponding bit in the dt_cmp_val0_l register is compared to determine flit-match.
0b1The corresponding bit in the dt_cmp_val0_l register is not compared to determine flit-match.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_cmp_mask0_l register bit assignments.

Figure 3-45 dt_cmp_mask0_l register bit assignments
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The following table shows the dt_cmp_mask0_l register bit assignments.

Table 3-56 dt_cmp_mask0_l register bit assignments

Bits Name Access Reset value Function
[63] - RAZ/WI 0x0 Reserved
[62:0] dt_cmp_mask0_l RW 0x0

Flit mapping:

val/mask[43:0]ADDR
val/mask[45:44]CCID
val/mask[47:46]DATAID
val/mask[55:48]DBID
val/mask[56:56]DYNPCRD
val/mask[57:57]EXCL
val/mask[58:58]EXPCOMPACK
val/mask[59:59]LIKELYSHARED
val/mask[62:60]LPID

Debug and Trace Comparison High Mask 0 register

The dt_cmp_mask0_h register is at offset 0x0328. Its characteristics are:

Purpose

Mask used for qualification of most-significant bits of watchpoint comparison:

0b0The corresponding bit in the dt_cmp_val0_h register is compared to determine flit-match.
0b1The corresponding bit in the dt_cmp_val0_h register is not compared to determine flit-match.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_cmp_mask0_h register bit assignments.

Figure 3-46 dt_cmp_mask0_h register bit assignments
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The following table shows the dt_cmp_mask0_h register bit assignments.

Table 3-57 dt_cmp_mask0_h register bit assignments

Bits Name Access Reset value Function
[63:60] - RAZ/WI 0x0 Reserved
[59:0] dt_cmp_mask0_h RW 0x0

Flit mapping:

val/mask[3:0]MEMATTR
val/mask[4:4]MEMATTR_ALLOCATE
val/mask[5:5]MEMATTR_CACHEABLE
val/mask[6:6]MEMATTR_DEVICE
val/mask[7:7]MEMATTR_EARLYWRACK
val/mask[8:8]NS
val/mask[13:9]OPCODE
val/mask[15:14]ORDER
val/mask[17:16]PCRDTYPE
val/mask[21:18]QOS
val/mask[24:22]RESP
val/mask[26:25]RESPERR
val/mask[30:27]RSVDC
val/mask[33:31]SIZE
val/mask[35:34]SNPATTR
val/mask[36:36]SNPATTR_SNOOPABLE
val/mask[37:37]SNPATTR_SNPDOMAIN
val/mask[44:38]SRCID
val/mask[51:45]TGTID
val/mask[59:52]TXNID

Debug and Trace Comparison Low Value 1 register

The dt_cmp_val1_l register is at offset 0x0350. Its characteristics are:

PurposeValue used for least-significant bits of watchpoint comparison.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_cmp_val1_l register bit assignments.

Figure 3-47 dt_cmp_val1_l register bit assignments
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The following table shows the dt_cmp_val1_l register bit assignments.

Table 3-58 dt_cmp_val1_l register bit assignments

Bits Name Access Reset value Function
[63] - RAZ/WI 0x0 Reserved
[62:0] dt_cmp_val1_l RW 0x0

Flit mapping:

val/mask[43:0]ADDR
val/mask[45:44]CCID
val/mask[47:46]DATAID
val/mask[55:48]DBID
val/mask[56:56]DYNPCRD
val/mask[57:57]EXCL
val/mask[58:58]EXPCOMPACK
val/mask[59:59]LIKELYSHARED
val/mask[62:60]LPID

Debug and Trace Comparison High Value 1 register

The dt_cmp_val1_h register is at offset 0x0358. Its characteristics are:

PurposeValue used for most-significant bits of watchpoint comparison.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_cmp_val1_h register bit assignments.

Figure 3-48 dt_cmp_val1_h register bit assignments
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The following table shows the dt_cmp_val1_h register bit assignments.

Table 3-59 dt_cmp_val1_h register bit assignments

Bits Name Access Reset value Function
[63:60] - RAZ/WI 0x0 Reserved
[59:0] dt_cmp_val1_h RW 0x0

Flit mapping:

val/mask[3:0]MEMATTR
val/mask[4:4]MEMATTR_ALLOCATE
val/mask[5:5]MEMATTR_CACHEABLE
val/mask[6:6]MEMATTR_DEVICE
val/mask[7:7]MEMATTR_EARLYWRACK
val/mask[8:8]NS
val/mask[13:9]OPCODE
val/mask[15:14]ORDER
val/mask[17:16]PCRDTYPE
val/mask[21:18]QOS
val/mask[24:22]RESP
val/mask[26:25]RESPERR
val/mask[30:27]RSVDC
val/mask[33:31]SIZE
val/mask[35:34]SNPATTR
val/mask[36:36]SNPATTR_SNOOPABLE
val/mask[37:37]SNPATTR_SNPDOMAIN
val/mask[44:38]SRCID
val/mask[51:45]TGTID
val/mask[59:52]TXNID

Debug and Trace Comparison Low Mask 1 register

The dt_cmp_mask1_l register is at offset 0x0360. Its characteristics are:

Purpose

Mask used for qualification of least-significant bits of watchpoint comparison:

0b0The corresponding bit in the dt_cmp_val1_l register is compared to determine flit-match.
0b1The corresponding bit in the dt_cmp_val1_l register is not compared to determine flit-match.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_cmp_mask1_l register bit assignments.

Figure 3-49 dt_cmp_mask1_l register bit assignments
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The following table shows the dt_cmp_mask1_l register bit assignments.

Table 3-60 dt_cmp_mask1_l register bit assignments

Bits Name Access Reset value Function
[63] - RAZ/WI 0x0 Reserved
[62:0] dt_cmp_mask1_l RW 0x0

Flit mapping:

val/mask[43:0]ADDR
val/mask[45:44]CCID
val/mask[47:46]DATAID
val/mask[55:48]DBID
val/mask[56:56]DYNPCRD
val/mask[57:57]EXCL
val/mask[58:58]EXPCOMPACK
val/mask[59:59]LIKELYSHARED
val/mask[62:60]LPID

Debug and Trace Comparison High Mask 1 register

The dt_cmp_mask1_h register is at offset 0x0368. Its characteristics are:

Purpose

Mask used for qualification of most-significant bits of watchpoint comparison:

0b0The corresponding bit in the dt_cmp_val1_h register is compared to determine flit-match.
0b1The corresponding bit in the dt_cmp_val1_h register is not compared to determine flit-match.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_cmp_mask1_h register bit assignments.

Figure 3-50 dt_cmp_mask1_h register bit assignments
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The following table shows the dt_cmp_mask1_h register bit assignments.

Table 3-61 dt_cmp_mask1_h register bit assignments

Bits Name Access Reset value Function
[63:60] - RAZ/WI 0x0 Reserved
[59:0] dt_cmp_mask1_h RW 0x0

Flit mapping:

val/mask[3:0]MEMATTR
val/mask[4:4]MEMATTR_ALLOCATE
val/mask[5:5]MEMATTR_CACHEABLE
val/mask[6:6]MEMATTR_DEVICE
val/mask[7:7]MEMATTR_EARLYWRACK
val/mask[8:8]NS
val/mask[13:9]OPCODE
val/mask[15:14]ORDER
val/mask[17:16]PCRDTYPE
val/mask[21:18]QOS
val/mask[24:22]RESP
val/mask[26:25]RESPERR
val/mask[30:27]RSVDC
val/mask[33:31]SIZE
val/mask[35:34]SNPATTR
val/mask[36:36]SNPATTR_SNOOPABLE
val/mask[37:37]SNPATTR_SNPDOMAIN
val/mask[44:38]SRCID
val/mask[51:45]TGTID
val/mask[59:52]TXNID

Debug and Trace Control register, dt_control

The dt_control register is at offset 0x0370. Its characteristics are:

PurposeControls the debug and trace settings.
Usage constraintsBefore writing bit[0], all other debug and trace configuration registers must be programmed. After debug and trace is enabled by writing bit[0], no other debug and trace configuration registers must be modified.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_control register bit assignments.

Figure 3-51 dt_control register bit assignments
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The following table shows the dt_control register bit assignments.

Table 3-62 dt_control register bit assignments

Bits Name Access Reset value Function
[63:28] - RAZ/WI 0x0 Reserved
[27:24] wp1_event_count RW 0x0 The number of events that watchpoint 1 must observe before the trigger can be generated. The cumulative count is reset when the watchpoint is disabled by writing 0 to the dt_enable bit of this register.
[23:20] wp0_event_count RW 0x0 The number of events that watchpoint 0 must observe before the trigger can be generated. The cumulative count is reset when the watchpoint is disabled by writing 0 to the dt_enable bit of this register.
[19:16] wp1_arm_sel RW 0xF

Selects the event source that is used to arm the watchpoint 1 trigger. Any active event from the source activates the watchpoint 1 trigger logic. Arming is deactivated after reset or when the watchpoint is disabled by writing 0 to the dt_enable bit of this register:

0x0DTBus[0].
0x1DTBus[1].
0x2DTBus[2].
0x3DTBus[3].
0x4DTBus[4].
0x5DTBus[5].
0x6DTBus[6].
0x7DTBus[7].
0x8Watchpoint 0 trigger.
0x9-0xEReserved.
0xFAlways armed.
[15:12] wp0_arm_sel RW 0xF

Selects the event source that is used to arm the watchpoint 0 trigger. Any active event from the source activates the watchpoint 0 trigger logic. Arming is deactivated after reset or when the watchpoint is disabled by writing 0 to the dt_enable bit of this register:

0x0DTBus[0].
0x1DTBus[1].
0x2DTBus[2].
0x3DTBus[3].
0x4DTBus[4].
0x5DTBus[5].
0x6DTBus[6].
0x7DTBus[7].
0x8Watchpoint 1 trigger.
0x9-0xEReserved.
0xFAlways armed.
[11] txnid_copyover RW 0

Controls whether the TXNID field from the watchpoint 0 input flit must be copied over to watchpoint 1. The copy happens the first time when watchpoint 0 is triggered:

1Enabled.
0Disabled.
[10:3] dt_bus_or_mode RW 0x0

Controls whether the bit on the DT bus must OR the input from the previous XP, instead of muxing in the current result:

0b0OR mode disabled.
0b1OR mode enabled.
[2:1] dt_ss_capture_en RW 0x0

Control snapshotting of flit on first watchpoint match. See the following table for field values.

Any field not defined for the flit is written as 0.

[0] dt_enable RW 0

Enable debug watchpoint and PMU capability:

0Disabled.
1Enabled.

See Usage constraints in register characteristics description.

Table 3-63 Snapshot capture enable values

Value DWM 1 DWM 0
0b00 Disabled Disabled
0b01 Disabled Enabled
0b10 Enabled Disabled
0b11 Enabled Enabled

Debug and Trace Status register

The dt_status register is at offset 0x0378. Its characteristics are:

PurposeIndicates the debug and trace status.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_status register bit assignments.

Figure 3-52 dt_status register bit assignments
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The following table shows the dt_status register bit assignments.

Table 3-64 dt_status register bit assignments

Bits Name Access Reset value Function
[63:2] - RAZ/WI 0x0 Reserved
[1:0] sscapture_status RO 0b00 Indication that a flit has been snapshotted because of watchpoint match. See the following table for field values.

Table 3-65 Snapshot capture status values

Value DWM 1 DWM 0
0b00 Not captured Not captured
0b01 Not captured Captured
0b10 Captured Not captured
0b11 Captured Captured

Debug and Trace Status Clear register

The dt_status_clr register is at offset 0x0380. Its characteristics are:

PurposeClears the debug and trace status.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the dt_status_clr register bit assignments.

Figure 3-53 dt_status_clr register bit assignments
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The following table shows the dt_status_clr register bit assignments.

Table 3-66 dt_status_clr register bit assignments

Bits Name Access Reset value Function
[63:2] - RAZ/WI 0x0 Reserved
[1:0] dt_status_clr WO 0b00 Write 1 to clear the DT status bit. See the following table for field values.

Table 3-67 Snapshot capture status values

Value DWM 1 DWM 0
0b00 Not cleared Not cleared
0b01 Not cleared Cleared
0b10 Cleared Not cleared
0b11 Cleared Cleared

Error Syndrome 0 register, XP

The err_syndrome_reg0 register is at offset 0x0400. Its characteristics are:

PurposeIndicates the XP parity error log information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the err_syndrome_reg0 register bit assignments.

Figure 3-54 err_syndrome_reg0 register bit assignments
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The following table shows the err_syndrome_reg0 register bit assignments.

Table 3-68 err_syndrome_reg0 register bit assignments

Bits Name Access Reset value Function
[63] err_extnd RO 0 Error extended.
[62] first_err_vld RO 0 First error valid.
[61:60] err_class RO 0b00 Error classification.
[59] mult_err RO 0 Multiple errors.
[58:43] corrected_err_count RO 0x0 Corrected error count.
[42:22] - RAZ/WI 0x0 Reserved
[21:8] - RAZ/WI 0x0 Reserved
[7:6] - RAZ/WI 0b00 Reserved
[5:0] err_id RO 0x0

Error identifier:

Bit[0]Download device port number.
Bits[2:1]

Download source:

00Bus 0.
01Bus 1.
10Bypass.
Bits[5:3]

Channel type:

000REQ.
001RSP.
010SNP.
011DATA.
111DATB.

XP Error Syndrome Clear register

The err_syndrome_clr register is at offset 0x0480. Its characteristics are:

PurposeClears the error log in the Error Syndrome 0 register.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the err_syndrome_clr register bit assignments.

Figure 3-55 err_syndrome_clr register bit assignments
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The following table shows the err_syndrome_clr register bit assignments.

Table 3-69 err_syndrome_clr register bit assignments

Bits Name Access Reset value Function
[63] - RAZ/WI 0 Reserved
[62] first_err_vld_clr WO 0 Clears the first_err_vld bit in the Error Syndrome 0 register
[61:60] - RAZ/WI 0b00 Reserved
[59] mult_err_clr WO 0 Clears the mult_err bit in the Error Syndrome 0 register
[58:0] - RAZ/WI 0x0 Reserved

Auxiliary Control register, XP

The aux_ctl register is at offset 0x0500. Its characteristics are:

PurposeControls various modes of operation.
Usage constraintsThis register can be modified only with prior written permission from ARM.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the aux_ctl register bit assignments.

Figure 3-56 aux_ctl register bit assignments
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The following table shows the aux_ctl register bit assignments.

Table 3-70 aux_ctl register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:24] byp_prio_weight RW 0x10 The number of cycles that a stalled bypass request waits until being prioritized over ring downloads.

Note:

The priority weight value must be set greater than the respin latency, that is, the number of clocks it takes to traverse the ring once. This is to avoid starvation of a bus message when it contends with a port bypass message.
[23:16] dnload_starv_thresh RW 0x04 The number of cycles a flit, that is unable to download, waits until reserving a download flit-buffer in the target XP.
[15:8] upload_starv_thresh RW 0x20 The number of cycles a flit, that is unable to upload, waits until reserving a ring-slot.
[7:5] Reserved RAZ/WI 0b000 -
[4] dat_parity_resperr_disable RW 0 DAT parity signaling RespErr disable.
[3] parity_irq_disable RW 0 Disable parity interrupt. This bit is applicable only in configurations that include ring parity.
[2] qpc_en RW 0 Enable QoS priority class based upload arbitration.
[1] dnload_starv_en RW 1 Enable download starvation prevention mechanism.
[0] upload_starv_en RW 1 Enable upload starvation prevention mechanism.

Byte Parity Error Injection register, XP

The byte_par_err_inj register is at offset 0x0508. Its characteristics are:

PurposeSelects a byte lane, within the 128-bit data bus, and injects a byte parity error on the next DAT flit.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the byte_par_err_inj register bit assignments.

Figure 3-57 byte_par_err_inj register bit assignments
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The following table shows the byte_par_err_inj register bit assignments.

Table 3-71 byte_par_err_inj register bit assignments

Bits Name Access Reset value Function
[63:4] - RAZ/WI 0x0 Reserved.
[3:0] byte_parity_err_inj WO -

Selects the byte lane, within the 128-bit data bus, where the XP injects a byte parity error. The XP injects a byte parity error on the next DAT flit that it passes.

The bit values are:

0b0000Inserts a parity error in bits[7:0].
0b0001Inserts a parity error in bits[15:8].
0b0010Inserts a parity error in bits[23:16].
0b1111Inserts a parity error in bits[127:120].

If multiple writes occur to this field before the XP passes a DAT flit, then the XP uses the initial value that is written and ignores the subsequent writes.

PMU Event Select register, XP

The pmu_event_sel register is at offset 0x0600. Its characteristics are:

PurposeSelects the Performance Monitoring Unit (PMU) events to be counted.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the pmu_event_sel register bit assignments.

Figure 3-58 pmu_event_sel register bit assignments
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The following table shows the pmu_event_sel register bit assignments.

Table 3-72 pmu_event_sel register bit assignments

Bits Name Access Reset value Function
[63:28] - RAZ/WI 0x0 Reserved
[27:21] pmu_event3_id RW 0x0

PMU Event 3 ID. The event is specified as a 7-bit ID with the following encodings:

Event_ID[27:25]

Channel type:

0b000REQ.
0b001RSP.
0b010SNP.
0b011DAT or DATA.
0b111DATB.
Event_ID[24]

Bus number:

0Bus 0.
1Bus 1. This is not applicable for the SNP channel.
Event_ID[23:21]

Event specifier:

0b000Null (no event).
0b001Set H-bit, signaled when this XP sets the H-bit.
0b010Set S-bit, signaled when this XP sets the S-bit.
0b011Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP channel.
0b100No TknV, signaled when this XP transmits a valid packet.
0b101-0b111Reserved.
[20:14] pmu_event2_id RW 0x0

PMU Event 2 ID. The event is specified as a 7-bit ID with the following encodings:

Event_ID[20:18]Channel type.
Event_ID[17]Bus number.
Event_ID[16:14]Event specifier.

See pmu_event3_id in this table for more information.

[13:7] pmu_event1_id RW 0x0

PMU Event 1 ID. The event is specified as a 7-bit ID with the following encodings:

Event_ID[13:11]Channel type.
Event_ID[10]Bus number.
Event_ID[9:7]Event specifier.

See pmu_event3_id in this table for more information.

[6:0] pmu_event0_id RW 0x0

PMU Event 0 ID. The event is specified as a 7-bit ID with the following encodings:

Event_ID[6:4]Channel type.
Event_ID[3]Bus number.
Event_ID[2:0]Event specifier.

See pmu_event3_id in this table for more information.

XP Identification register

The oly_xp_oly_id register is at offset 0xFF00. Its characteristics are:

PurposeContains the component identification information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-5 XP register summary.

The following figure shows the oly_xp_oly_id register bit assignments.

Figure 3-59 oly_xp_oly_id register bit assignments
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The following table shows the oly_xp_oly_id register bit assignments.

Table 3-73 oly_xp_oly_id register bit assignments

Bits Name Access Reset value Function
[63:15] - RAZ/WI 0x0 Reserved
[14:8] node_id RO Reset value is specific to each XP The node ID of the XP
[7:5] - RAZ/WI 0b000 Reserved
[4:0] oly_id RO 0x8 Indicates that this node is an XP
a See Table 3-52 dt_cfg field values for the dt_cfg field values.
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