3.3.1 MN register descriptions

This section lists the MN registers.

Secure Access register

The secure_access register is at offset 0x0000. Its characteristics are:

PurposePermits a Non-secure access request to access Secure registers.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the secure_access register bit assignments.

Figure 3-1 secure_access register bit assignments
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The following table shows the secure_access register bit assignments.

Table 3-11 secure_access register bit assignments

Bits Name Access Reset value Description
[63:3] - RAZ/WI 0x0 Reserved
[2] secure_debug_disable RW 0

Secure debug disable:

1If SPNIDEN is HIGH then Secure events are monitored by the PMU.
0Secure events are monitored by the PMU.
[1] - RAZ/WI 0 Reserved
[0] secure_access RW 0

Secure access:

1Enables Non-secure access to Secure registers.
0Precludes Non-secure access to Secure registers.

Error Interrupt Status register

The errint_status register is at offset 0x0008. Its characteristics are:

PurposeDisables interrupts and disables corrected error logging.
Usage constraintsOnly accessible by Secure accesses. Bits[3:0] control whether writes to bits[7:4] are successful.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the errint_status register bit assignments.

Figure 3-2 errint_status register bit assignments
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The following table shows the errint_status register bit assignments.

Table 3-12 errint_status register bit assignments

Bits Name Access Reset value Description
[63:8] - RAZ/WI 0x0 Reserved
[7:4] data_int_status RW 0x0

A read returns the interrupt disable status:

  • 0 = Interrupt type is enabled.
  • 1 = Interrupt type is disabled.

A write enables or disables the interrupt, provided the corresponding write enable (bits[3:0]) is set:

Bit[7]0 = Enable interrupt for PMU event. 1 = Disable interrupt for PMU event.
Bit[6]0 = Enable interrupt for corrected error. 1 = Disable interrupt for corrected error.
Bit[5]0 = Enable interrupt for all errors, including corrected errors. 1 = Disable interrupt for all errors, including corrected errors.
Bit[4]0 = Enable the INTREQ interrupt. 1 = Disable the INTREQ interrupt. If the interrupt is asserted, then it also deasserts the INTREQ interrupt signal.
[3:0] mask_int_status RW 0x0

These bits are write enables for the data_int_status bits, [7:4]. Always Read-As-Zero.

Bit[3]Set to 1, to enable writes to data_int_status[7], the PMU event interrupt mask.
Bit[2]Set to 1, to enable writes to data_int_status[6], the Corrected error mask.
Bit[1]Set to 1, to enable writes to data_int_status[5], the All error mask.
Bit[0]Set to 1, to enable writes to data_int_status[4], the INTREQ interrupt enable.

RN-F Node ID register

The oly_rnf_nodeid_list register is at offset 0x0180. Its characteristics are:

PurposeA bit vector that indicates the RN-Fs in the system. Each bit in the vector corresponds to a nodeID, with a 1'b1 indicating an RN-F is present at that nodeID.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_rnf_nodeid_list register bit assignments.

Figure 3-3 oly_rnf_nodeid_list register bit assignments
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The following table shows the oly_rnf_nodeid_list register bit assignments.

Table 3-13 oly_rnf_nodeid_list register bit assignments

Bits Name Access Reset value Description
[63:0] oly_rnf_nodeid_list RO 0x8A2 (6XP/2HNF) Bit vector of NodeIDs for RN-Fs. The value that is returned depends on the setting of the RNFEN_NID<x>. The reset value that is shown is for a CCN with a fully populated configuration of RN-Fs.
0x8282 (8XP/4HNF)

RN-I Node ID register

The oly_rni_nodeid_list register is at offset 0x0190. Its characteristics are:

PurposeA bit vector that indicates the RN-Is in the system. Each bit in the vector corresponds to a nodeID, with a 1'b1 indicating an RN-I is present at that nodeID.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_rni_nodeid_list register bit assignments.

Figure 3-4 oly_rni_nodeid_list register bit assignments
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The following table shows the oly_rni_nodeid_list register bit assignments.

Table 3-14 oly_rni_nodeid_list register bit assignments

Bits Name Access Reset value Description
[63:0] oly_rni_nodeid_list RO Value depends on customer configuration Bit vector of NodeIDs for RN-Is

RN-D Node ID register

The oly_rnidvm_nodeid_list register is at offset 0x01A0. Its characteristics are:

PurposeA bit vector that indicates the RN-Ds in the system. Each bit in the vector corresponds to a nodeID, with a 1'b1 indicating an RN-D is present at that nodeID.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_rnidvm_nodeid_list register bit assignments.

Figure 3-5 oly_rnidvm_nodeid_list register bit assignments
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The following table shows the oly_rnidvm_nodeid_list register bit assignments.

Table 3-15 oly_rnidvm_nodeid_list register bit assignments

Bits Name Access Reset value Description
[63:0] oly_rnidvm_nodeid_list RO Value depends on customer configuration Bit vector of NodeIDs for RN-D bridges

HN-F Node ID register

The oly_hnf_nodeid_list register is at offset 0x01B0. Its characteristics are:

PurposeA bit vector that indicates the HN-Fs in the system. Each bit in the vector corresponds to a nodeID, with a 1'b1 indicating an HN-F is present at that nodeID.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_hnf_nodeid_list register bit assignments.

Figure 3-6 oly_hnf_nodeid_list register bit assignments
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The following table shows the oly_hnf_nodeid_list register bit assignments.

Table 3-16 oly_hnf_nodeid_list register bit assignments

Bits Name Access Reset value Description
[63:0] oly_hnf_nodeid_list RO 0x208 (6XP/2HNF) Bit vector of NodeIDs for HN-Fs.
0x2828 (8XP/4HNF)

HN-I Node ID register

The oly_hni_nodeid_list register is at offset 0x01C0. Its characteristics are:

PurposeA bit vector that indicates the HN-Is in the system. Each bit in the vector corresponds to a nodeID, with a 1'b1 indicating an HN-I is present at that nodeID.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_hni_nodeid_list register bit assignments.

Figure 3-7 oly_hni_nodeid_list register bit assignments
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The following table shows the oly_hni_nodeid_list register bit assignments.

Table 3-17 oly_hni_nodeid_list register bit assignments

Bits Name Access Reset value Description
[63:0] oly_hni_nodeid_list RO 0x1 (6XP/2HNF) Bit vector of NodeIDs for HN‑Is.
0x1 (8XP/4HNF)

SN Node ID register

The oly_sn_nodeid_list register is at offset 0x01D0. Its characteristics are:

PurposeA bit vector that indicates the SNs in the system. Each bit in the vector corresponds to a nodeID, with a 1'b1 indicating an SN is present at that nodeID.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_sn_nodeid_list register bit assignments.

Figure 3-8 oly_sn_nodeid_list register bit assignments
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The following table shows the oly_sn_nodeid_list register bit assignments.

Table 3-18 oly_sn_nodeid_list register bit assignments

Bits Name Access Reset value Description
[63:0] oly_sn_nodeid_list RO 0x104 (6XP/2HNF) Bit vector of NodeIDs for SN‑F ports
0x1414 (8XP/4HNF)

Component List [63:0] register

The oly_cfg_comp_list_63_0 register is at offset 0x01E0. Its characteristics are:

PurposeIndicates the presence of valid components corresponding to configuration register regions 0-63.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_cfg_comp_list_63_0 register bit assignments.

Figure 3-9 oly_cfg_comp_list_63_0 register bit assignments
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The following table shows the oly_cfg_comp_list_63_0 register bit assignments.

Table 3-19 oly_cfg_comp_list_63_0 register bit assignments

Bits Name Access Reset value Description
[63:0] oly_cfg_comp_list_63_0 RO Value depends on customer configuration Indicates the presence of valid components corresponding to configuration register regions 0-63

Component List [127:64] register

The oly_cfg_comp_list_127_64 register is at offset 0x01E8. Its characteristics are:

PurposeIndicates the presence of valid components corresponding to configuration register regions 64-127.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_cfg_comp_list_127_64 register bit assignments.

Figure 3-10 oly_cfg_comp_list_127_64 register bit assignments
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The following table shows the oly_cfg_comp_list_127_64 register bit assignments.

Table 3-20 oly_cfg_comp_list_127_64 register bit assignments

Bits Name Access Reset value Description
[63:0] oly_cfg_comp_list_127_64 RO Value depends on customer configuration Indicates the presence of valid components corresponding to configuration register regions 64-127

Component List [191:128] register

The oly_cfg_comp_list_191_128 register is at offset 0x01F0. Its characteristics are:

PurposeIndicates the presence of valid components corresponding to configuration register regions 128-191.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_cfg_comp_list_191_128 register bit assignments.

Figure 3-11 oly_cfg_comp_list_191_128 register bit assignments
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The following table shows the oly_cfg_comp_list_191_128 register bit assignments.

Table 3-21 oly_cfg_comp_list_191_128 register bit assignments

Bits Name Access Reset value Description
[63:0] oly_cfg_comp_list_191_128 RO Value depends on customer configuration Indicates the presence of valid components corresponding to configuration register regions 128-191

Component List [255:192] register

The oly_cfg_comp_list_255_192 register is at offset 0x01F8. Its characteristics are:

PurposeIndicates the presence of valid components corresponding to configuration register regions 192-255.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_cfg_comp_list_255_192 register bit assignments.

Figure 3-12 oly_cfg_comp_list_255_192 register bit assignments
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The following table shows the oly_cfg_comp_list_255_192 register bit assignments.

Table 3-22 oly_cfg_comp_list_255_192 register bit assignments

Bits Name Access Reset value Description
[63:0] oly_cfg_comp_list_255_192 RO Value depends on customer configuration Indicates the presence of valid components corresponding to regions configuration register 192-255

DVM Domain Control register

The dvm_domain_ctl register is at offset 0x0200. Its characteristics are:

PurposeA bit vector that defines the RNs that must be sent and must respond to a DVMOp snoop from the MN. Each bit in the vector corresponds to a nodeID, and when a bit is set to 1 it indicates that an RN in the DVM domain is present at that nodeID.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the dvm_domain_ctl register bit assignments.

Figure 3-13 dvm_domain_ctl register bit assignments
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The following table shows the dvm_domain_ctl register bit assignments.

Table 3-23 dvm_domain_ctl register bit assignments

Bits Name Access Reset value Description
[63:0] dvm_domain_ctl RO 0x0 Bit vector of NodeIDs for all RN‑Fs and RN‑Is that are active in the DVM domain. These RNs are devices that receive and must respond to DVMOps.

DVM Domain Control Set register

The dvm_domain_ctl_set register is at offset 0x0210. Its characteristics are:

PurposeA bit vector that controls which nodeIDs of RNs to insert into the active DVM domain. Each bit in the vector corresponds to a nodeID.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the dvm_domain_ctl_set register bit assignments.

Figure 3-14 dvm_domain_ctl_set register bit assignments
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The following table shows the dvm_domain_ctl_set register bit assignments.

Table 3-24 dvm_domain_ctl_set register bit assignments

Bits Name Access Reset value Description
[63:0] dvm_domain_ctl_set WO 0x0 Bit vector of NodeIDs of RNs to insert into the active DVM domain. Completion of insertion, results in the indicated RNs receiving and being required to respond to DVMOps.

DVM Domain Control Clear register

The dvm_domain_ctl_clr register is at offset 0x0220. Its characteristics are:

PurposeA bit vector that controls which nodeIDs of RNs to remove from the active DVM domain. Each bit in the vector corresponds to a nodeID.
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the dvm_domain_ctl_clr register bit assignments.

Figure 3-15 dvm_domain_ctl_clr register bit assignments
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The following table shows the dvm_domain_ctl_clr register bit assignments.

Table 3-25 dvm_domain_ctl_clr register bit assignments

Bits Name Access Reset value Description
[63:0] dvm_domain_ctl_clr WO 0x0 Bit vector of NodeIDs of RNs to remove from the active DVM domain. Completion of removal, results in the indicated RNs no longer receiving nor being required to respond to DVMOps.

Error Signal Valid [63:0] register

The err_sig_val_63_0 register is at offset 0x0300. Its characteristics are:

PurposeIndicates an error in nodes [63:0].
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the err_sig_val_63_0 register bit assignments.

Figure 3-16 err_sig_val_63_0 register bit assignments
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The following table shows the err_sig_val_63_0 register bit assignments.

Table 3-26 err_sig_val_63_0 register bit assignments

Bits Name Access Reset value Description
[63:40] - RAZ/WI 0x0 Reserved
[39:32] err_sig_val_hnf RO 0x0 Indicates an HN-F error
[31:20] - RAZ/WI 0x0 Reserved
[19:16] err_sig_val_sn RO 0x0 Indicates an SN error
[15:10] - RAZ/WI 0x0 Reserved
[9:8] err_sig_val_hni RO 0x0 Indicates an HN-I error
[7:2] - RAZ/WI 0x0 Reserved
[1] err_sig_val_dt RO 0 Indicates a DT error
[0] - RO 0 Reserved

Error Signal Valid [127:64] register

The err_sig_val_127_64 register is at offset 0x0308. Its characteristics are:

PurposeIndicates an error in nodes [127:64].
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the err_sig_val_127_64 register bit assignments.

Figure 3-17 err_sig_val_127_64 register bit assignments
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The following table shows the err_sig_val_127_64 register bit assignments.

Table 3-27 err_sig_val_127_64 register bit assignments

Bits Name Access Reset value Description
[63:1] - RAZ/WI 0x0 Reserved
[0] err_sig_val_xp RO 0 Indicates an XP error

Error Signal Valid [191:128] register

The err_sig_val_191_128 register is at offset 0x0310. Its characteristics are:

PurposeIndicates an error in nodes [191:128].
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the err_sig_val_191_128 register bit assignments.

Figure 3-18 err_sig_val_191_128 register bit assignments
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The following table shows the err_sig_val_191_128 register bit assignments.

Table 3-28 err_sig_val_191_128 register bit assignments

Bits Name Access Reset value Description
[63:32] - RAZ/WI 0x0 Reserved
[31:0] err_sig_val_rn RO 0x0 Indicates an RN interface error

Error Type Value [31:0] register

The err_type_31_0 register is at offset 0x0320. Its characteristics are:

PurposeIndicates the type of error in nodes [31:0].
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the err_type_31_0 register bit assignments.

Figure 3-19 err_type_31_0 register bit assignments
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The following table shows the err_type_31_0 register bit assignments.

Table 3-29 err_type_31_0 register bit assignments

Bits Name Access Reset value Description
[63:40] - RAZ/WI 0x0 Reserved
[39:32] err_type_sn RO 0x0

Indicates the type of SN error:

0b01 = Correctable error.

0b11 = Fatal error.

Within this field, the slave nodes are:

  • SN0 = bits[33:32].
  • SN1 = bits[35:34].
  • SN2 = bits[37:36], for 8XP/4HNF only.
  • SN3 = bits[39:38], for 8XP/4HNF only.
[31:20] - RAZ/WI 0x0 Reserved
[19:16] err_type_hni RO 0x0

Indicates the type of HN-I error:

0b01 = Correctable error.

0b11 = Fatal error.

Within this field, the HN-I nodes are:

  • HN-I0 = bits[17:16].
  • Reserved = bits[19:18].
[15:4] - RAZ/WI 0x0 Reserved
[3:2] err_type_dt RO 0x0

Indicates the type of DT error:

0b01 = Correctable error.

0b11 = Fatal error.

[1:0] - RO 0x0 Reserved

Error Type Value [63:32] register

The err_type_63_32 register is at offset 0x0328. Its characteristics are:

PurposeIndicates the type of error in nodes [63:32].
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the err_type_63_32 register bit assignments.

Figure 3-20 err_type_63_32 register bit assignments
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The following table shows the err_type_63_32 register bit assignments.

Table 3-30 err_type_63_32 register bit assignments

Bits Name Access Reset value Description
[63:16] - RAZ/WI 0x0 Reserved
[15:0] err_type_hnf RO 0x0

Indicates the type of HN-F error:

0b01 = Correctable error.

0b11 = Fatal error.

Within this field, the HN-F nodes are:

  • HN-F0 = bits[1:0].
  • HN-F1 = bits[3:2].
  • HN-F2 = bits[5:4], for 8XP/4HNF only.
  • HN-F3 = bits[7:6], for 8XP/4HNF only.

Bits[15:8] are Reserved.

Error Type Value [95:64] register

The err_type_95_64 register is at offset 0x0330. Its characteristics are:

PurposeIndicates the type of error in nodes [95:64].
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the err_type_95_64 register bit assignments.

Figure 3-21 err_type_95_64 register bit assignments
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The following table shows the err_type_95_64 register bit assignments.

Table 3-31 err_type_95_64 register bit assignments

Bits Name Access Reset value Description
[63:2] - RAZ/WI 0x0 Reserved
[1:0] err_type_xp RO 0b00

Indicates the type of XP error:

0b01 = Correctable error.

0b11 = Fatal error.

Error Type Value [159:128] register

The err_type_159_128 register is at offset 0x0340. Its characteristics are:

PurposeIndicates the type of error in nodes [159:128].
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the err_type_159_128 register bit assignments.

Figure 3-22 err_type_159_128 register bit assignments
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The following table shows the err_type_159_128 register bit assignments.

Table 3-32 err_type_159_128 register bit assignments

Bits Name Access Reset value Description
[63:0] err_type_rn RO 0x0

Indicates the type of RN-I interface error:

0b01 = Correctable error.

0b11 = Fatal error.

Within this field, the RN-I nodes are:

  • RN-I0 = bits[1:0].
  • RN-I1 = bits[3:2].
  • RN-I2 = bits[5:4].

Bits[63:6] are Reserved.

Peripheral ID 4 and Peripheral ID 5 register

The periph_id_4_periph_id_5 register is at offset 0x0FD0. Its characteristics are:

PurposeContains Peripheral ID 4 in bits[31:0] and Peripheral ID 5 in bits[63:32].
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the periph_id_4_periph_id_5 register bit assignments.

Figure 3-23 periph_id_4_periph_id_5 register bit assignments
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The following table shows the periph_id_4_periph_id_5 register bit assignments.

Table 3-33 periph_id_4_periph_id_5 register bit assignments

Bits Name Access Reset value Description
[63:8] - RAZ/WI 0x0 Reserved
[7:4] size RO 0xC Log2 of the number of 4KB blocks occupied by the interface
[3:0] des_2 RO 0x4 JEP106 continuation code [3:0]

Peripheral ID 6 and Peripheral ID 7 register

The periph_id_6_periph_id_7 register is at offset 0x0FD8. Its characteristics are:

PurposeContains Peripheral ID 6 in bits[31:0] and Peripheral ID 7 in bits[63:32].
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the periph_id_6_periph_id_7 register bit assignments.

Figure 3-24 periph_id_6_periph_id_7 register bit assignments
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The following table shows the periph_id_6_periph_id_7 register bit assignments.

Table 3-34 periph_id_6_periph_id_7 register bit assignments

Bits Name Access Reset value Description
[63:0] - RAZ/WI 0x0 Reserved

Peripheral ID 0 and Peripheral ID 1 register

The periph_id_0_periph_id_1 register is at offset 0x0FE0. Its characteristics are:

PurposeContains Peripheral ID 0 in bits[31:0] and Peripheral ID 1 in bits[63:32].
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the periph_id_0_periph_id_1 register bit assignments.

Figure 3-25 periph_id_0_periph_id_1 register bit assignments
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The following table shows the periph_id_0_periph_id_1 register bit assignments.

Table 3-35 periph_id_0_periph_id_1 register bit assignments

Bits Name Access Reset value Description
[63:40] - RAZ/WI 0x0 Reserved
[39:36] des_0 RO 0xB JEP106 identity code [3:0]
[35:32] part_1 RO 0x4 Part number [11:8]
[31:8] - RAZ/WI 0x0 Reserved
[7:0] part_0 RO 0x30 Part number [7:0]

Peripheral ID 2 and Peripheral ID 3 register

The periph_id_2_periph_id_3 register is at offset 0x0FE8. Its characteristics are:

PurposeContains Peripheral ID 2 in bits[31:0] and Peripheral ID 3 in bits[63:32].
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the periph_id_2_periph_id_3 register bit assignments.

Figure 3-26 periph_id_2_periph_id_3 register bit assignments
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The following table shows the periph_id_2_periph_id_3 register bit assignments.

Table 3-36 periph_id_2_periph_id_3 register bit assignments

Bits Name Access Reset value Description
[63:40] - RAZ/WI 0x0 Reserved
[39:32] cmod RO 0x0 Customer and manufacturer revision.
[31:8] - RAZ/WI 0x0 Reserved
[7:4] revision RO 0x0

Revision:

0x0r0p0.
[3] jedec RO 1 JEDEC JEP106 identity code is used.
[2:0] des_1 RO 0b011 JEP106 identity code [6:4].

Component ID 0 and Component ID 1 register

The component_id_0_component_id_1 register is at offset 0x0FF0. Its characteristics are:

PurposeContains Component ID 0 in bits[31:0] and Component ID 1 in bits[63:32].
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the component_id_0_component_id_1 register bit assignments.

Figure 3-27 component_id_0_component_id_1 register bit assignments
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The following table shows the component_id_0_component_id_1 register bit assignments.

Table 3-37 component_id_0_component_id_1 register bit assignments

Bits Name Access Reset value Description
[63:40] - RAZ/WI 0x0 Reserved
[39:36] class RO 0xF Component class
[35:32] prmbl_1 RO 0x0 Component ID 1
[31:8] - RAZ/WI 0x0 Reserved
[7:0] prmbl_0 RO 0x0D Component ID 0

Component ID 2 and Component ID 3 register

The component_id_2_component_id_3 register is at offset 0x0FF8. Its characteristics are:

PurposeContains Component ID 2 in bits[31:0] and Component ID 3 in bits[63:32].
Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the component_id_2_component_id_3 register bit assignments.

Figure 3-28 component_id_2_component_id_3 register bit assignments
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The following table shows the component_id_2_component_id_3 register bit assignments.

Table 3-38 component_id_2_component_id_3 register bit assignments

Bits Name Access Reset value Description
[63:40] - RAZ/WI 0x0 Reserved
[39:32] prmbl_3 RO 0xB1 Component ID 3
[31:8] - RAZ/WI 0x0 Reserved
[7:0] prmbl_2 RO 0x05 Component ID 2

MN Identification register

The oly_mn_oly_id register is at offset 0xFF00. Its characteristics are:

PurposeContains the component identification information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-4 MN register summary.

The following figure shows the oly_mn_oly_id register bit assignments.

Figure 3-29 oly_mn_oly_id register bit assignments
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The following table shows the oly_mn_oly_id register bit assignments.

Table 3-39 oly_mn_oly_id register bit assignments

Bits Name Access Reset value Description
[63:15] - RAZ/WI 0x0 Reserved
[14:8] node_id RO 0x0 The node ID of the MN
[7:5] - RAZ/WI 0b000 Reserved
[4:0] oly_id RO 0x1 Node-type identifier
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