2.14.4 P-Channel

Each power domain in the CCN-502 includes a separate P-Channel for control of that domain. The P‑Channel is a simple power-controller-to-device interface that manages device power states.

The P-Channel interface has the following features:

This protocol is a generic way to request a transition to a particular state using a request-acknowledge 4‑phase handshake. The specific state transitions of the device under management are not restricted by the P-Channel protocol, but might be restricted by the capabilities of the device, as they are in the CCN-502.

The P-Channel contains the following signals, where * is an identifier for a power domain:

PREQ_*Indicates a request for a power state transition.
PSTATE_*[n−1:0]The power state to which a transition is requested.
PACCEPT_*Indicates acknowledgment of the power state transition and completion of the power state transition in the device.
PDENY_*Indicates denial of the power state transition.
PACTIVE_*A hint signal that indicates opportunistic power state transitions such as dynamic retention modes. The signal name and state transition hint are defined by the device implementation.

The following figure shows the signals and their connections.

Figure 2-16 P-Channel interface with ACTIVE hint
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The following sections describe the P-Channel:

P-Channel protocol

P-Channel protocol rules control P-Channel state transition.

The P-Channel protocol is as follows:

  • PREQ can only transition from LOW to HIGH when PACCEPT and PDENY are both LOW.
  • PREQ can only transition from HIGH to LOW when either:
    • PACCEPT is HIGH and PDENY is LOW.
    • PACCEPT is LOW and PDENY is HIGH.
  • PSTATE can only transition when PREQ, PACCEPT, and PDENY are LOW. The signal transition must be guaranteed to be complete, and metastability resolved, when PREQ is asserted or RESETn is deasserted.
  • PACCEPT can only transition from LOW to HIGH when PREQ is HIGH and PDENY is LOW.
  • PACCEPT can only transition from HIGH to LOW when PREQ is LOW and PDENY is LOW.
  • PDENY can only transition from LOW to HIGH when PREQ is HIGH and PACCEPT is LOW.
  • PDENY can only transition from HIGH to LOW when PREQ is LOW and PACCEPT is LOW.

P-Channel state transition

This section describes the 4-phase handshake of the P-Channel.

The following figure shows a basic state transition timing diagram.

Figure 2-17 State transition timing diagram
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The state transition uses the following 4-phase handshake:

  1. The power controller drives the required state on PSTATE.
  2. When it is guaranteed that this signal is stable, the power controller asserts PREQ.
  3. The device asserts PACCEPT. If the state transition requires any actions from the device, such as cache initialization, the device must complete the action before it asserts PACCEPT.
  4. The power controller responds by deasserting PREQ, and the device finishes by deasserting PACCEPT.

P-Channel on device reset

This section shows how to initialize the power state of a power domain.

The following figure shows the state initialization on reset. Certain device power states might power down the control logic. When powering this control logic back on, the power controller must indicate the state that the device must power up. The device detects the required state by sampling PSTATE when RESETn deasserts. The PSTATE inputs must be asserted before the deassertion of reset and remain after the deassertion of RESETn to allow reset propagation. The power controller must ensure that the reset sequence has completed before transitioning PSTATE, otherwise the device might sample an undetermined value.

Figure 2-18 Reset state initialization
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P-Channel interfaces

This section describes the various P-Channel interfaces in the CCN-502.

The CCN-502 power states are managed by the following P-Channel interfaces:

LOGICControls the power state of the logic domain.
SFControls the power state of the snoop filter.
L3RAM0Controls the power state of the L3 tag/data RAMs way[7:0].
L3RAM1Controls the power state of the L3 tag/data RAMs way[15:0].
DEVAn optional interface that controls the power state of the optional DMC and processor DSSBs. These interfaces can be controlled uniquely, and are used to control the ON/OFF power states of the CCN502_SNF_DSSB and CCN502_RNF_DSSB blocks, after the respective DMC and processor cluster devices are powered down.

The P-Channel for the snoop filter, L3-RAM-Hi, and L3-RAM-Lo power domains is communicated to the 2 (6XP/2HNF) or 4 (8XP/4HNF) HN-Fs by the PCCB. The PCCB acts as a distributor of P-Channel requests to the 2 (6XP/2HNF) or 4 (8XP/4HNF) HN-Fs and aggregator of P-Channel responses from the 2 (6XP/2HNF) or 4 (8XP/4HNF) HN-Fs.

Power state transitions that require control of multiple P-Channels

The power controller must control multiple P-Channels for some power state transitions.

As Figure 2-15 Power state transitions shows, some state transition arcs require P-state changes in multiple P-Channels, for example, to transition from NOL3 to FAM. There is no requirement for all P-Channels to simultaneously request the P-state change as indicated for these transitions, because the CCN-502 has internal control interlocks to ensure that it only allows transitions between valid power states. Therefore, the P-Channels can be independently controlled and might not be concurrently asserted, and the CCN-502 ensures that a required power state transition occurs only after receiving the last P-state request that leads to a valid power state.

The control mechanism ensures that transitions only occur between valid states. However, the control mechanism might enable transitions from one valid state to another by taking an unintended arc through another valid state, for example, in the transition from NOL3 to FAM. It is possible to transition between these two states in any of the following four sequences, depending on the perceived ordering of the P-Channel P-state transitions:

NOL3 to FAM
The sequence is L3RAM1PSTATE=ON to L3RAM0PSTATE=ON to SFPSTATE=ON.
NOL3 to SFONLY to HAM to FAM
The sequence is SFPSTATE=ON to L3RAM0PSTATE=ON to L3RAM1PSTATE=ON.
NOL3 to SFONLY to FAM
The sequence is SFPSTATE=ON to L3RAM1PSTATE=ON to L3RAM0PSTATE=ON.
NOL3 to HAM to FAM
The sequence is L3RAM0PSTATE=ON to SFPSTATE=ON to L3RAM1PSTATE=ON.

Although these are all valid state transition sequences and the CCN-502 guarantees correct functionality for any of these sequences, the most efficient sequence is the first. All other sequences result in multiple initialization sequences of some of the L3/SF RAMs. For the most efficient sequence, the P-state transition requests must be seen at the receiver in the order that guarantees exactly the required state transition. Although the P-Channel does not include a specific way of determining the order of arrival, the CCN-502 timing requirements are such that, if the P-Channel PREQ assertions on different P-Channels are separated by 15 or more clock cycles, those requests are guaranteed to be observed in that order at the receiver. For this reason, it is possible, and recommended, that you construct the P-Channel control mechanisms to ensure the most efficient transition between power states in the CCN-502.

Transitions to and from shutdown states

The power controller must satisfy certain conditions to enable the various shutdown state transitions.

There are two types of shutdown state transitions:

Transitions to a shutdown state
  • NOL3 to OFF.
  • SFONLY to SFONLY static retention.
  • HAM to HAM static retention.
  • FAM to FAM static retention.
Transitions from a shutdown state
  • SFONLY static retention to SFONLY.
  • HAM static retention to HAM.
  • FAM static retention to FAM.

The power controller must not perform any power transitions when the control logic is powered off. This means that:

  • When transitioning from a shutdown state to a functional state, which includes a transition of LOGICPSTATE from OFF to ON, that transition must have been initiated and must be complete, that is, it must have received PACCEPT, before a transition of any of the other P-Channels can be initiated. This ensures that the logic required to complete transition of the other P-Channels is powered up to enable the transition.
  • When transitioning to a shutdown state, which includes a transition of LOGICPSTATE from ON to OFF, transitions of all other P-Channels, as applicable, must have been initiated and must be complete, that is, must have received PACCEPT, before the transition of the LOGIC P-Channel can be initiated. This ensures that the logic required to complete transition of other P-Channels is powered up to enable the transition.

    In addition, when transitioning to a shutdown state, the control logic issues a PDENY to a PREQ on the LOGIC P-Channel if there is any outstanding traffic in the CCN-502. After receiving the PDENY, it is the responsibility of the power controller to undo the P-Channel transitions that have already been accepted. For example, in response to a PDENY on the LOGIC P-Channel during a HAM to HAM static retention transition, the power controller must then issue P-Channel transitions to SFPSTATE=ON and L3RAM0PSTATE=ON.

    The PDENY response only occurs if there is ongoing activity in the CCN-502, therefore it is possible to avoid the PDENY response if the CCN-502 is fully quiesced, that is, contains no in-flight transactions of any kind, before the power controller initiates a LOGIC P-Channel request to enter a shutdown state.

PSTATE on reset

Not all PSTATEs are available for the power controller to use when the control logic is reset.

The CCN-502 enables entry into four power states when the control logic is reset, with the following restrictions on the power controller:

SFONLY static retention
  • LOGICPSTATE = OFF.
  • SFPSTATE = MEM_RET.
  • L3RAM0PSTATE = OFF.
  • L3RAM1PSTATE = OFF.
HAM static retention
  • LOGICPSTATE = OFF.
  • SFPSTATE = MEM_RET.
  • L3RAM0PSTATE = MEM_RET.
  • L3RAM1PSTATE = OFF.
FAM static retention
  • LOGICPSTATE = OFF.
  • SFPSTATE = MEM_RET.
  • L3RAM0PSTATE = MEM_RET.
  • L3RAM1PSTATE = MEM_RET.
FAM
  • LOGICPSTATE = ON.
  • SFPSTATE = ON.
  • L3RAM0PSTATE = ON.
  • L3RAM1PSTATE = ON.

All PSTATE signals must be asserted at deassertion of reset. All PREQ signals must be LOW at the deassertion of reset. Any P-state values other than those described here are invalid and can result in unpredictable behavior.

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