2.13.1 Clocking

The following sections describe the CCN-502 clocking microarchitecture:

Asynchronous communication

To close timing in a CCN-502 system, there are various classes of timing paths to consider.

The timing paths are:

  • Paths within a CCN-502 logic block.
  • Paths from a device to and from a CCN-502 XP upload and download port.
  • Paths between XPs.

The CCN-502 provides straightforward convergence of timing paths within a logic block, to avoid timing issues.

For the device/XP communication path, each XP optionally includes a device/XP source-synchronous asynchronous bridge (DSSB). This enables the device to run asynchronously to the CCN-502. The DSSBs can only exist in the XPs as the following figure shows, and the DSSBs exist in two distinct groups:

  • Those in XPs connected to memory controllers.
  • Those in XPs connected to processor compute clusters.

The inclusion or exclusion of each of these groups is independently optional. However, inclusion or exclusion occurs only at group granularity, that is, if a DSSB is present in a group, all DSSBs in that group must be present.

Each DSSB is implemented as two blocks:

  • A block in the XP that contains the CCN-502 power and clock domain functionality.
  • The other block contains the device domain clock and power functionality, which can be implemented in the device hierarchy.

The DSSB blocks connected to the processor compute clusters are the CCN502_RNF_DSSB, and the DSSB blocks connected to the memory controllers are the CCN502_SNF_DSSB.

The following figure shows a CCN-502 system with optional DSSBs.

Figure 2-8 CCN-502 system with optional DSSBs
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All asynchronous communication between CCN-502 and AMBA devices, for example, asynchronous communication between the CCN-502 interconnect and master I/O subsystem, are supported by existing AMBA asynchronous domain bridge products, such as the CoreLink ADB-400 AMBA Domain Bridge.

Clock domains

The CCN-502 has different clock domains depending on the options included in a particular implementation.

Figure 2-9 CCN-502 clock domain, fully synchronous shows the single clock domain in a CCN-502 interconnect without asynchronous capabilities or register slices.

Figure 2-9 CCN-502 clock domain, fully synchronous
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Figure 2-10 CCN-502 clock domains with optional DSSBs shows the multiple clock domains in a CCN-502 interconnect that includes the optional DSSBs for asynchronous communication with processor compute clusters or DMCs. Although most of the CCN-502 is clocked with a shared synchronous clock, the receive-FIFO logic in the respective DSSBs is clocked with the clock sent by the transmitting device, as required for source-synchronous communication. The CCN-502 does not place any requirements or constraints on the various processor or DMC clocks.

Figure 2-10 CCN-502 clock domains with optional DSSBs
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Because of the group-level granularity, that is, processor or DMC groups, at which the DSSBs are optionally included, there are three possible configurations when DSSBs are included:

  • Both processor and DMC DSSBs are included.
  • Only processor DSSBs are included.
  • Only DMC DSSBs are included.

The respective clock domain requirements of these three configurations change as required.

The clocking configurations in a CCN-502 interconnect that includes some or all of the optional protocol bridges are different from those described for the CCN-502 baseline configuration. The main difference between the two is that the inclusion of a protocol bridge on an XP device port prevents the inclusion of a DSSB on that device port. In other words, any asynchronous communication between an AMBA device and the CCN-502 interconnect through an optional protocol bridge must be provided by an existing AMBA asynchronous domain bridge, such as the CoreLink ADB-400 AMBA Domain Bridge.

Clock hierarchy

The clocking delivery and clock gating architecture is hierarchical.

Within the clock gating hierarchy, three levels of clocks are defined:

Global clocksThese are the clock inputs to the CCN-502 system. The global clocks that the SoC provides are likely to be controlled by an additional level of clock gating or clock control outside of the system. Although this is not a system requirement, the CCN-502 includes support for external clock control.
Regional clocksRegional clocks are created as an output of regional clock gaters that include a coarse enable for coarse-grained clock gating under idle or mostly idle conditions. This enables a higher level of power reduction than is possible using local clock gating, because the clock network between the regional and local gaters can be shut down using the regional gaters. The regional clock gaters are instantiated in and controlled by the CCN-502 RTL. The exact set of regional clocks is internal to the CCN-502 and is not described in this book.
Local clocksLocal clocks are created as an output of the local clock gaters that are controlled by fine-grained enables that the CCN-502 RTL creates. Local clocks are used to directly clock sequential elements in the CCN-502. The exact set of local clocks is internal to the CCN-502 and is not described in this book.

The following figure shows the clocking hierarchy.

Figure 2-11 Clocking hierarchy
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Global clocks

Global clock inputs for a specific configuration are a combination of the global clocks for the baseline configuration and those included for all applicable configuration options.

The number and types of global clock inputs depend on the configuration of the network, as follows:

Baseline
The baseline configuration contains a single synchronous clock domain for the entire CCN-502 system, and includes the following global clock input:
GCLK0Clock input for Domain 0, which, in this configuration, is defined as the entire CCN-502.
Optional DMC DSSB
When the optional DMC DSSBs are included, additional clock inputs and outputs are provided. In this configuration, the definition of Domain 0 is unchanged. In the following clock names, <x> represents the node ID of the Dynamic Memory Controller (DMC):
RXRSPGCLKCD_NID<x>Source-synchronous input clock that is used to receive the RSP flit from the DMC.
RXDATGCLKCD_NID<x>Source-synchronous input clock that is used to receive the DAT flit from the DMC.
TXREQGCLK_NID<x>Source-synchronous output clock that is used to send the REQ flit from the CCN-502 to the DMC.
TXDATGCLK_NID<x>Source-synchronous output clock that is used to send the DAT flit from the CCN-502 to the DMC.
Optional processor DSSB
When the optional processor DSSBs are included, additional clock inputs and outputs are provided. In this configuration, the definition of Domain 0 is unchanged. In the following clock names, <x> represents the node ID of the processor cluster:
RXREQGCLKCD_NID<x>Source-synchronous input clock that is used to receive the REQ flit from the processor cluster.
RXRSPGCLKCD_NID<x>Source-synchronous input clock that is used to receive the RSP flit from the processor cluster.
RXDATGCLKCD_NID<x>Source-synchronous input clock that is used to receive the DAT flit from the processor cluster.
TXRSPGCLK_NID<x>Source-synchronous output clock that is used to send the RSP flit from the CCN-502 to the processor cluster.
TXDATGCLK_NID<x>Source-synchronous output clock that is used to send the DAT flit from the CCN-502 to the processor cluster.
TXSNPGCLK_NID<x>Source-synchronous output clock that is used to send the SNP flit from the CCN-502 to the processor cluster.

The following table shows the possible clocking combinations in the CCN-502 system. In the clock names, <x> represents the node ID of the processor cluster or DMC.

Table 2-7 Clock domain options

Processor-DSSB DMC-DSSB Number of domains Global clock inputs
No No

1 (6XP/2HNF).

1 (8XP/4HNF).

GCLK0
No Yes

3 (6XP/2HNF).

5 (8XP/4HNF).

GCLK0

RXRSPGCLKCD_NID<x>, RXDATGCLKCD_NID<x>, TXREQGCLK_NID<x>, TXDATGCLK_NID<x>

Yes No

5 (6XP/2HNF).

5 (8XP/4HNF).

GCLK0

RXREQGCLKCD_NID<x>, RXRSPGCLKCD_NID<x>, RXDATGCLKCD_NID<x>, TXRSPGCLK_NID<x>, TXDATGCLK_NID<x>, TXSNPGCLK_NID<x>

Yes Yes

7 (6XP/2HNF).

9 (8XP/4HNF).

GCLK0

RXRSPGCLKCD_NID<x>, RXDATGCLKCD_NID<x>, TXREQGCLK_NID<x>, TXDATGCLK_NID<x>

RXREQGCLKCD_NID<x>, RXRSPGCLKCD_NID<x>, RXDATGCLKCD_NID<x>, TXRSPGCLK_NID<x>, TXDATGCLK_NID<x>, TXSNPGCLK_NID<x>

Clock enable inputs

The CCN-502 includes several clock enable inputs.

The clock enable input signals are:

ACLKEN_SThis input is present on each AMBA slave interface.
ACLKEN_MThis input is present on each AMBA master interface.
DCLKENThis input is present on the debug and trace STMHWEVENT interface.

All the clock enables, shown here as *CLKEN*, have identical functionality, enabling the respective interfaces with which they are included to run at integer fractions of GCLK0, that is, slower than GCLK0, ranging from 1:1 to 4:1. DCLKEN is limited to 2:1 to 4:1 integer fractions. This enables synchronous communication with slower SoC logic.

*CLKEN* asserts one GCLK0 cycle before the rising edge of SoC-CLK. SoC control logic can change the ratio of GCLK0 frequency to the SoC clock, SoC-CLK, frequency dynamically using *CLKEN*.

The following figure shows a timing example of *CLKEN* that changes the ratio of the frequency at which the relevant interface operates respective to GCLK0 from 3:1 to 1:1.

Figure 2-12 *CLKEN* with GCLK0:SoC-CLK ratio changing from 3:1 to 1:1
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Timing closure with register slices

The network provides register slices to assist during timing closure.

The CCN-502 includes the following optional register slices:

  • Device Register Slice (DRS), at the device/XP boundaries.

The slices are simple repeater-flop structures applied across the entire communication boundary. Register slices can only be used at a synchronously-clocked communication boundary, and a DRS cannot be used in conjunction with a DSSB. Any device/XP boundary can contain up to two back-to-back DRSs. Link-layer buffering for devices connected to the DRSs is automatically adjusted to handle the additional credit/response latency.

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