3.3.6 RN-I bridge register descriptions

Lists the RN-I registers.

Port S0 Control register, RN-I

The s0_port_control register is at offset 0x0008. Its characteristics are:

PurposeControls the port S0 AXI/ACE slave interface.
Usage constraintsOnly accessible by Secure accesses. Before writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s0_port_control register bit assignments.

Figure 3-127 s0_port_control register bit assignments
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The following table shows the s0_port_control register bit assignments.

Table 3-141 s0_port_control register bit assignments

Bits Name Access Reset value Function
[63:15] - RAZ/WI 0x0 Reserved
[14:4] s0_lpid_mask RW 0x0

S0 port LPID mask. Specifies the AXID bits to be reflected in the least significant bit of the LPID:

LPID[0]BitwiseOR (LPID mask AND AXID).
LPID[2:1]Port ID[1:0].
[3:2] - RW 0x0 Reserved
[1:0] - RAZ/WI 0x0 Reserved

Port S0 QoS Control register, RN-I

The s0_qos_control register is at offset 0x0010. Its characteristics are:

PurposeControls the QoS settings for the port S0 AXI/ACE slave interface.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s0_qos_control register bit assignments.

Figure 3-128 s0_qos_control register bit assignments
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The following table shows the s0_qos_control register bit assignments.

Table 3-142 s0_qos_control register bit assignments

Bits Name Access Reset value Function
[63:24] - RAZ/WI 0x0 Reserved
[23:20] s0_ar_qos_override RW 0x0 S0 port AR QoS override value.
[19:16] s0_aw_qos_override RW 0x0 S0 port AW QoS override value.
[15:8] - RAZ/WI 0x0 Reserved
[7] s0_ar_pqv_mode RW 0

Configures the mode of the QoS regulator during period mode for bandwidth regulation during read transactions:

0Normal mode. The QoS value is stable when the master is idle.
1Quiesce high mode. The QoS value tends to the maximum value when the master is idle.
[6] s0_aw_pqv_mode RW 0

Configures the mode of the QoS regulator during period mode for bandwidth regulation during write transactions:

0Normal mode. The QoS value is stable when the master is idle.
1Quiesce high mode. The QoS value tends to the maximum value when the master is idle.
[5] s0_ar_reg_mode RW 0

Configures the mode of the QoS regulator for read transactions:

0Latency mode.
1Period mode, for bandwidth regulation.
[4] s0_aw_reg_mode RW 0

Configures the mode of the QoS regulator for write transactions:

0Latency mode.
1Period mode, for bandwidth regulation.
[3] s0_ar_qos_override_en RW 0 S0 port AR QoS override enable. When set, this bit enables the QoS value on inbound AR transactions to be overridden.
[2] s0_aw_qos_override_en RW 0 S0 port AW QoS override enable. When set, this bit enables the QoS value on inbound AW transactions to be overridden.
[1] s0_ar_lat_en RW 0 S0 port AR QoS regulation enable. When set, this bit enables AR regulation.
[0] s0_aw_lat_en RW 0 S0 port AW QoS regulation enable. When set, this bit enables AW regulation.

Port S0 QoS Latency Target register, RN-I

The s0_qos_lat_tgt register is at offset 0x0018. Its characteristics are:

PurposeControls the QoS target latency, in cycles, for the regulation of reads and writes for port S0. A value of 0 corresponds to no regulation.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s0_qos_lat_tgt register bit assignments.

Figure 3-129 s0_qos_lat_tgt register bit assignments
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The following table shows the s0_qos_lat_tgt register bit assignments.

Table 3-143 s0_qos_lat_tgt register bit assignments

Bits Name Access Reset value Function
[63:28] - RAZ/WI 0x0 Reserved
[27:16] s0_ar_lat_tgt RW 0x0 S0 AR channel target latency
[15:12] - RAZ/WI 0x0 Reserved
[11:0] s0_aw_lat_tgt RW 0x0 S0 AW channel target latency

Port S0 QoS Latency Scale register, RN-I

The s0_qos_lat_scale register is at offset 0x0020. Its characteristics are:

PurposeControls the QoS target latency scale factor for reads and writes for port S0. It is coded for powers of 2 in the range 2–5 to 2–12.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s0_qos_lat_scale register bit assignments.

Figure 3-130 s0_qos_lat_scale register bit assignments
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The following table shows the s0_qos_lat_scale register bit assignments.

Table 3-144 s0_qos_lat_scale register bit assignments

Bits Name Access Reset value Function
[63:11] - RAZ/WI 0x0 Reserved
[10:8] s0_ar_lat_scale RW 0x0 S0 AR QoS scale factor, in powers of 2 in the range 2–5 to 2–12
[7:3] - RAZ/WI 0x0 Reserved
[2:0] s0_aw_lat_scale RW 0x0 S0 AW QoS scale factor, in powers of 2 in the range 2–5 to 2–12

Port S0 QoS Latency Range register, RN-I

The s0_qos_lat_range register is at offset 0x0028. Its characteristics are:

PurposeControls the QoS minimum and maximum values generated by the QoS latency regulator for reads and writes for port S0.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s0_qos_lat_range register bit assignments.

Figure 3-131 s0_qos_lat_range register bit assignments
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The following table shows the s0_qos_lat_range register bit assignments.

Table 3-145 s0_qos_lat_range register bit assignments

Bits Name Access Reset value Function
[63:28] - RAZ/WI 0x0 Reserved
[27:24] s0_ar_lat_max_qos RW 0x0 S0 AR QoS maximum value
[23:20] - RAZ/WI 0x0 Reserved
[19:16] s0_ar_lat_min_qos RW 0x0 S0 AR QoS minimum value
[15:12] - RAZ/WI 0x0 Reserved
[11:8] s0_aw_lat_max_qos RW 0x0 S0 AW QoS maximum value
[7:4] - RAZ/WI 0x0 Reserved
[3:0] s0_aw_lat_min_qos RW 0x0 S0 AW QoS minimum value

Port S1 Control register, RN-I

The s1_port_control register is at offset 0x0108. Its characteristics are:

PurposeControls the port S1 AXI/ACE slave interface.
Usage constraintsOnly accessible by Secure accesses. Before writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s1_port_control register bit assignments.

Figure 3-132 s1_port_control register bit assignments
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The following table shows the s1_port_control register bit assignments.

Table 3-146 s1_port_control register bit assignments

Bits Name Access Reset value Function
[63:15] - RAZ/WI 0x0 Reserved
[14:4] s1_lpid_mask RW 0x0

S1 port LPID mask. Specifies the AXID bits to be reflected in the least significant bit of the LPID:

LPID[0]BitwiseOR (LPID mask AND AXID).
LPID[2:1]Port ID[1:0].
[3:2] - RW 0x0 Reserved
[1:0] - RAZ/WI 0x0 Reserved

Port S1 QoS Control register, RN-I

The s1_qos_control register is at offset 0x0110. Its characteristics are:

PurposeControls the QoS settings for the port S1 AXI/ACE slave interface.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s1_qos_control register bit assignments.

Figure 3-133 s1_qos_control register bit assignments
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The following table shows the s1_qos_control register bit assignments.

Table 3-147 s1_qos_control register bit assignments

Bits Name Access Reset value Function
[63:24] - RAZ/WI 0x0 Reserved
[23:20] s1_ar_qos_override RW 0x0 S1 port AR QoS override value.
[19:16] s1_aw_qos_override RW 0x0 S1 port AW QoS override value.
[15:8] - RAZ/WI 0x0 Reserved
[7] s1_ar_pqv_mode RW 0

Configures the mode of the QoS regulator during period mode for bandwidth regulation during read transactions:

0Normal mode. The QoS value is stable when the master is idle.
1Quiesce high mode. The QoS value tends to the maximum value when the master is idle.
[6] s1_aw_pqv_mode RW 0

Configures the mode of the QoS regulator during period mode for bandwidth regulation during write transactions:

0Normal mode. The QoS value is stable when the master is idle.
1Quiesce high mode. The QoS value tends to the maximum value when the master is idle.
[5] s1_ar_reg_mode RW 0

Configures the mode of the QoS regulator for read transactions:

0Latency mode.
1Period mode, for bandwidth regulation.
[4] s1_aw_reg_mode RW 0

Configures the mode of the QoS regulator for write transactions:

0Latency mode.
1Period mode, for bandwidth regulation.
[3] s1_ar_qos_override_en RW 0 S1 port AR QoS override enable. When set, this bit enables the QoS value on inbound AR transactions to be overridden.
[2] s1_aw_qos_override_en RW 0 S1 port AW QoS override enable. When set, this bit enables the QoS value on inbound AW transactions to be overridden.
[1] s1_ar_lat_en RW 0 S1 port AR QoS regulation enable. When set, this bit enables AR regulation.
[0] s1_aw_lat_en RW 0 S1 port AW QoS regulation enable. When set, this bit enables AW regulation.

Port S1 QoS Latency Target register, RN-I

The s1_qos_lat_tgt register is at offset 0x0118. Its characteristics are:

PurposeControls the QoS target latency, in cycles, for the regulation of reads and writes for port S1. A value of 0 corresponds to no regulation.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s1_qos_lat_tgt register bit assignments.

Figure 3-134 s1_qos_lat_tgt register bit assignments
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The following table shows the s1_qos_lat_tgt register bit assignments.

Table 3-148 s1_qos_lat_tgt register bit assignments

Bits Name Access Reset value Function
[63:28] - RAZ/WI 0x0 Reserved
[27:16] s1_ar_lat_tgt RW 0x0 S1 AR channel target latency
[15:12] - RAZ/WI 0x0 Reserved
[11:0] s1_aw_lat_tgt RW 0x0 S1 AW channel target latency

Port S1 QoS Latency Scale register, RN-I

The s1_qos_lat_scale register is at offset 0x0120. Its characteristics are:

PurposeControls the QoS target latency scale factor for reads and writes for port S1. It is coded for powers of 2 in the range 2–5 to 2–12.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s1_qos_lat_scale register bit assignments.

Figure 3-135 s1_qos_lat_scale register bit assignments
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The following table shows the s1_qos_lat_scale register bit assignments.

Table 3-149 s1_qos_lat_scale register bit assignments

Bits Name Access Reset value Function
[63:11] - RAZ/WI 0x0 Reserved
[10:8] s1_ar_lat_scale RW 0x0 S1 AR QoS scale factor, in powers of 2 in the range 2–5 to 2–12
[7:3] - RAZ/WI 0x0 Reserved
[2:0] s1_aw_lat_scale RW 0x0 S1 AW QoS scale factor, in powers of 2 in the range 2–5 to 2–12

Port S1 QoS Latency Range register, RN-I

The s1_qos_lat_range register is at offset 0x0128. Its characteristics are:

PurposeControls the QoS minimum and maximum values generated by the QoS latency regulator for reads and writes for port S1.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s1_qos_lat_range register bit assignments.

Figure 3-136 s1_qos_lat_range register bit assignments
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The following table shows the s1_qos_lat_range register bit assignments.

Table 3-150 s1_qos_lat_range register bit assignments

Bits Name Access Reset value Function
[63:28] - RAZ/WI 0x0 Reserved
[27:24] s1_ar_lat_max_qos RW 0x0 S1 AR QoS maximum value
[23:20] - RAZ/WI 0x0 Reserved
[19:16] s1_ar_lat_min_qos RW 0x0 S1 AR QoS minimum value
[15:12] - RAZ/WI 0x0 Reserved
[11:8] s1_aw_lat_max_qos RW 0x0 S1 AW QoS maximum value
[7:4] - RAZ/WI 0x0 Reserved
[3:0] s1_aw_lat_min_qos RW 0x0 S1 AW QoS minimum value

Port S2 Control register, RN-I

The s2_port_control register is at offset 0x0208. Its characteristics are:

PurposeControls the port S2 AXI/ACE slave interface.
Usage constraintsOnly accessible by Secure accesses. Before writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s2_port_control register bit assignments.

Figure 3-137 s2_port_control register bit assignments
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The following table shows the s2_port_control register bit assignments.

Table 3-151 s2_port_control register bit assignments

Bits Name Access Reset value Function
[63:15] - RAZ/WI 0x0 Reserved
[14:4] s2_lpid_mask RW 0x0

S2 port LPID mask. Specifies the AXID bits to be reflected in the least significant bit of the LPID:

LPID[0]BitwiseOR (LPID mask AND AXID).
LPID[2:1]Port ID[1:0].
[3:2] - RW 0x0 Reserved
[1:0] - RAZ/WI 0x0 Reserved

Port S2 QoS Control register, RN-I

The s2_qos_control register is at offset 0x0210. Its characteristics are:

PurposeControls the QoS settings for the port S2 AXI/ACE slave interface.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s2_qos_control register bit assignments.

Figure 3-138 s2_qos_control register bit assignments
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The following table shows the s2_qos_control register bit assignments.

Table 3-152 s2_qos_control register bit assignments

Bits Name Access Reset value Function
[63:24] - RAZ/WI 0x0 Reserved
[23:20] s2_ar_qos_override RW 0x0 S2 port AR QoS override value.
[19:16] s2_aw_qos_override RW 0x0 S2 port AW QoS override value.
[15:8] - RAZ/WI 0x0 Reserved
[7] s2_ar_pqv_mode RW 0

Configures the mode of the QoS regulator during period mode for bandwidth regulation during read transactions:

0Normal mode. The QoS value is stable when the master is idle.
1Quiesce high mode. The QoS value tends to the maximum value when the master is idle.
[6] s2_aw_pqv_mode RW 0

Configures the mode of the QoS regulator during period mode for bandwidth regulation during write transactions:

0Normal mode. The QoS value is stable when the master is idle.
1Quiesce high mode. The QoS value tends to the maximum value when the master is idle.
[5] s2_ar_reg_mode RW 0

Configures the mode of the QoS regulator for read transactions:

0Latency mode.
1Period mode, for bandwidth regulation.
[4] s2_aw_reg_mode RW 0

Configures the mode of the QoS regulator for write transactions:

0Latency mode.
1Period mode, for bandwidth regulation.
[3] s2_ar_qos_override_en RW 0 S2 port AR QoS override enable. When set, this bit enables the QoS value on inbound AR transactions to be overridden.
[2] s2_aw_qos_override_en RW 0 S2 port AW QoS override enable. When set, this bit enables the QoS value on inbound AW transactions to be overridden.
[1] s2_ar_lat_en RW 0 S2 port AR QoS regulation enable. When set, this bit enables AR regulation.
[0] s2_aw_lat_en RW 0 S2 port AW QoS regulation enable. When set, this bit enables AW regulation.

Port S2 QoS Latency Target register, RN-I

The s2_qos_lat_tgt register is at offset 0x0218. Its characteristics are:

PurposeControls the QoS target latency, in cycles, for the regulation of reads and writes for port S2. A value of 0 corresponds to no regulation.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s2_qos_lat_tgt register bit assignments.

Figure 3-139 s2_qos_lat_tgt register bit assignments
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The following table shows the s2_qos_lat_tgt register bit assignments.

Table 3-153 s2_qos_lat_tgt register bit assignments

Bits Name Access Reset value Function
[63:28] - RAZ/WI 0x0 Reserved
[27:16] s2_ar_lat_tgt RW 0x0 S2 AR channel target latency
[15:12] - RAZ/WI 0x0 Reserved
[11:0] s2_aw_lat_tgt RW 0x0 S2 AW channel target latency

Port S2 QoS Latency Scale register, RN-I

The s2_qos_lat_scale register is at offset 0x0220. Its characteristics are:

PurposeControls the QoS target latency scale factor for reads and writes for port S1. It is coded for powers of 2 in the range 2–5 to 2–12.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s2_qos_lat_scale register bit assignments.

Figure 3-140 s2_qos_lat_scale register bit assignments
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The following table shows the s2_qos_lat_scale register bit assignments.

Table 3-154 s2_qos_lat_scale register bit assignments

Bits Name Access Reset value Function
[63:11] - RAZ/WI 0x0 Reserved
[10:8] s2_ar_lat_scale RW 0x0 S2 AR QoS scale factor, in powers of 2 in the range 2–5 to 2–12
[7:3] - RAZ/WI 0x0 Reserved
[2:0] s2_aw_lat_scale RW 0x0 S2 AW QoS scale factor, in powers of 2 in the range 2–5 to 2–12

Port S2 QoS Latency Range register, RN-I

The s2_qos_lat_range register is at offset 0x0228. Its characteristics are:

PurposeControls the QoS minimum and maximum values generated by the QoS latency regulator for reads and writes for port S2.
Usage constraintsBefore writing this register, all previous transactions from any devices connected to this AMBA port must be complete and no transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the s2_qos_lat_range register bit assignments.

Figure 3-141 s2_qos_lat_range register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the s2_qos_lat_range register bit assignments.

Table 3-155 s2_qos_lat_range register bit assignments

Bits Name Access Reset value Function
[63:28] - RAZ/WI 0x0 Reserved
[27:24] s2_ar_lat_max_qos RW 0x0 S2 AR QoS maximum value
[23:20] - RAZ/WI 0x0 Reserved
[19:16] s2_ar_lat_min_qos RW 0x0 S2 AR QoS minimum value
[15:12] - RAZ/WI 0x0 Reserved
[11:8] s2_aw_lat_max_qos RW 0x0 S2 AW QoS maximum value
[7:4] - RAZ/WI 0x0 Reserved
[3:0] s2_aw_lat_min_qos RW 0x0 S2 AW QoS minimum value

RN-I Auxiliary Control register

The aux_ctl register is at offset 0x0500. Its characteristics are:

PurposeControls various modes of operation.
Usage constraintsOnly accessible by Secure accesses. Before writing this register, all previous transactions from any device connected to this device port must be complete and no other transactions can be initiated until the write to this register is complete.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the aux_ctl register bit assignments.

Figure 3-142 aux_ctl register bit assignments
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The following table shows the aux_ctl register bit assignments.

Table 3-156 aux_ctl register bit assignments

Bits Name Access Reset value Function
[63:6] - RAZ/WI 0x0 Reserved
[5] force_rd_rqo RW 0 Forces all reads from the RN-I to be sent with the Request Order bit set and this ensures ordered allocation of read data buffers in the RN-I.
[4] wuo RW 0

Used for acceleration of coherent ordered writes, and is particularly useful for PCIe traffic. This bit can be set for only one RN-I in the system. The reset value for this bit is 0 for all RN-I components in the system.

[3] wfc RW 0 Enables waiting for Comp before the dependent transaction is dispatched.
[2] cg_disable RW 0 Clock gating disable. When set, this bit disables clock gating.
[1] qpc_en RW 0 QPC enable. When set, this bit enables QoS based scheduling using two QoS priority classes, QoS15 and non-QoS15.
[0] ar_byp_en RW 1 AR bypass enable. Enables bypass path in the AR pipeline.

PMU Event Select register, RN-I

The pmu_event_sel register is at offset 0x0600. Its characteristics are:

PurposeSelects the PMU events to be counted.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the pmu_event_sel register bit assignments.

Figure 3-143 pmu_event_sel register bit assignments
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The following table shows the pmu_event_sel register bit assignments.

Table 3-157 pmu_event_sel register bit assignments

Bits Name Access Reset value Function
[63:16] - RAZ/WI 0x0 Reserved
[15:12] pmu_event3_id RW 0x0

PMU Event 3 ID. The event is specified as a 4-bit ID with the following encodings:

0b0000Null (no event).
0b0001S0 RDataBeats.
0b0010S1 RDataBeats.
0b0011S2 RDataBeats.
0b0100RXDAT flits received.
0b0101TXDAT flits sent.
0b0110Total TXREQ flits sent.
0b0111Retried TXREQ flits sent.
0b1000RRT full.
0b1001WRT full.
0b1010Replayed TXREQ flits.

All other values are Reserved.

[11:8] pmu_event2_id RW 0x0

PMU Event 2 ID.

See pmu_event3_id in this table for more information.

[7:4] pmu_event1_id RW 0x0

PMU Event 1 ID.

See pmu_event3_id in this table for more information.

[3:0] pmu_event0_id RW 0x0

PMU Event 0 ID.

See pmu_event3_id in this table for more information.

RN-I Identification register

The oly_rni_oly_id register is at offset 0xFF00. Its characteristics are:

PurposeContains the component identification information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-9 RN-I bridge register summary.

The following figure shows the oly_rni_oly_id register bit assignments.

Figure 3-144 oly_rni_oly_id register bit assignments
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The following table shows the oly_rni_oly_id register bit assignments.

Table 3-158 oly_rni_oly_id register bit assignments

Bits Name Access Reset value Function
[63:15] - RAZ/WI 0x0 Reserved
[14:8] node_id RO Value is specific to each RN-I bridge The node ID of the RN-I bridge
[7:5] - RAZ/WI 0b000 Reserved
[4:0] oly_id RO 0x16 Indicates that this node is an RN-I bridge that supports 3 ACE-Lite interfaces
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