3.3.5 Debug event module register descriptions

This section lists the DEM registers.

Active DSM register

The active_dsm register is at offset 0x0000. Its characteristics are:

PurposeSpecifies the IDs of the XP containing the watchpoints that are driving the respective bits of the DTBus.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the active_dsm register bit assignments.

Figure 3-95 active_dsm register bit assignments
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The following table shows the active_dsm register bit assignments.

Table 3-109 active_dsm register bit assignments

Bits Name Access Reset value Function
[63:56] dsm_id7 RW 0x0 XP ID of XP driving DTBus[7]
[55:48] dsm_id6 RW 0x0 XP ID of XP driving DTBus[6]
[47:40] dsm_id5 RW 0x0 XP ID of XP driving DTBus[5]
[39:32] dsm_id4 RW 0x0 XP ID of XP driving DTBus[4]
[31:24] dsm_id3 RW 0x0 XP ID of XP driving DTBus[3]
[23:16] dsm_id2 RW 0x0 XP ID of XP driving DTBus[2]
[15:8] dsm_id1 RW 0x0 XP ID of XP driving DTBus[1]
[7:0] dsm_id0 RW 0x0 XP ID of XP driving DTBus[0]

Trigger Control register

The trigger_ctl register is at offset 0x0008. Its characteristics are:

PurposeControls the trigger operation.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the trigger_ctl register bit assignments.

Figure 3-96 trigger_ctl register bit assignments
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The following table shows the trigger_ctl register bit assignments.

Table 3-110 trigger_ctl register bit assignments

Bits Name Access Reset value Function
[63:16] - RAZ/WI 0x0 Reserved
[15:8] trigger_sel RW 0x0 Enable DTBus bits to be used for DBGWATCHTRIG assertion
[7:1] - RAZ/WI 0x0 Reserved
[0] trigger_en RW 0 Enables DBGWATCHTRIG

Trigger Status register

The trigger_status register is at offset 0x0010. Its characteristics are:

PurposeIndicates the trigger status.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the trigger_status register bit assignments.

Figure 3-97 trigger_status register bit assignments
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The following table shows the trigger_status register bit assignments.

Table 3-111 trigger_status register bit assignments

Bits Name Access Reset value Function
[63:8] - RAZ/WI 0x0 Reserved
[7:0] trigger_status RO 0x0 Indicates which DT bus bits caused the DBGWATCHTRIGREQ assertion

Trigger Status Clear register

The trigger_status_clr register is at offset 0x0018. Its characteristics are:

PurposeClears the trigger status.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the trigger_status_clr register bit assignments.

Figure 3-98 trigger_status_clr register bit assignments
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The following table shows the trigger_status_clr register bit assignments.

Table 3-112 trigger_status_clr register bit assignments

Bits Name Access Reset value Function
[63:8] - RAZ/WI 0x0 Reserved
[7:0] trigger_status_clr WO 0x0 Write 1 to clear corresponding bit of trigger_status register

Timer Value register

The timer_val register is at offset 0x0020. Its characteristics are:

PurposeControls the timer value.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the timer_val register bit assignments.

Figure 3-99 timer_val register bit assignments
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The following table shows the timer_val register bit assignments.

Table 3-113 timer_val register bit assignments

Bits Name Access Reset value Function
[63:16] - RAZ/WI 0x0 Reserved
[15:0] timer_val RW 0x0 Number of cycles delay between debug event from DT bus and DBGWATCHTRIG assertion

Debug and Trace Control register, dt_ctl

The dt_ctl register is at offset 0x0028. Its characteristics are:

PurposeControls the debug and trace features.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the dt_ctl register bit assignments.

Figure 3-100 dt_ctl register bit assignments
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The following table shows the dt_ctl register bit assignments.

Table 3-114 dt_ctl register bit assignments

Bits Name Access Reset value Function
[63:1] - RAZ/WI 0x0 Reserved
[0] dt_en RW 0 Enables the debug and trace features

Debug Identification register

The dbg_id register is at offset 0x0080. Its characteristics are:

PurposeIndicates the debug features.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the dbg_id register bit assignments.

Figure 3-101 dbg_id register bit assignments
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The following table shows the dbg_id register bit assignments.

Table 3-115 dbg_id register bit assignments

Bits Name Access Reset value Function
[63:24] - RAZ/WI 0x0 Reserved
[23:16] num_pmucntr RO 0x09 Number of PMU counters
[15:8] num_watchpoint RO 0x16 Number of watchpoints
[7:0] dbg_id RO 0x00 for a 4-bit RSDVC configuration, 0x02 for an 8-bit RSVDC configuration Debug ID register

PMU Event Counter 0 register

The pmevcnt0 register is at offset 0x0100. Its characteristics are:

PurposeIndicates the value of PMU event counter 0.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcnt0 register bit assignments.

Figure 3-102 pmevcnt0 register bit assignments
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The following table shows the pmevcnt0 register bit assignments.

Table 3-116 pmevcnt0 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcnt0 RW 0x0 Value of PMU event counter 0

PMU Event Counter 1 register

The pmevcnt1 register is at offset 0x0108. Its characteristics are:

PurposeIndicates the value of PMU event counter 1.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcnt1 register bit assignments.

Figure 3-103 pmevcnt1 register bit assignments
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The following table shows the pmevcnt1 register bit assignments.

Table 3-117 pmevcnt1 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcnt1 RW 0x0 Value of PMU event counter 1

PMU Event Counter 2 register

The pmevcnt2 register is at offset 0x0110. Its characteristics are:

PurposeIndicates the value of PMU event counter 2.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcnt2 register bit assignments.

Figure 3-104 pmevcnt2 register bit assignments
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The following table shows the pmevcnt2 register bit assignments.

Table 3-118 pmevcnt2 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcnt2 RW 0x0 Value of PMU event counter 2

PMU Event Counter 3 register

The pmevcnt3 register is at offset 0x0118. Its characteristics are:

PurposeIndicates the value of PMU event counter 3.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcnt3 register bit assignments.

Figure 3-105 pmevcnt3 register bit assignments
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The following table shows the pmevcnt3 register bit assignments.

Table 3-119 pmevcnt3 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcnt3 RW 0x0 Value of PMU event counter 3

PMU Event Counter 4 register

The pmevcnt4 register is at offset 0x0120. Its characteristics are:

PurposeIndicates the value of PMU event counter 4.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcnt4 register bit assignments.

Figure 3-106 pmevcnt4 register bit assignments
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The following table shows the pmevcnt4 register bit assignments.

Table 3-120 pmevcnt4 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcnt4 RW 0x0 Value of PMU event counter 4

PMU Event Counter 5 register

The pmevcnt5 register is at offset 0x0128. Its characteristics are:

PurposeIndicates the value of PMU event counter 5.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcnt5 register bit assignments.

Figure 3-107 pmevcnt5 register bit assignments
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The following table shows the pmevcnt5 register bit assignments.

Table 3-121 pmevcnt5 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcnt5 RW 0x0 Value of PMU event counter 5

PMU Event Counter 6 register

The pmevcnt6 register is at offset 0x0130. Its characteristics are:

PurposeIndicates the value of PMU event counter 6.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcnt6 register bit assignments.

Figure 3-108 pmevcnt6 register bit assignments
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The following table shows the pmevcnt6 register bit assignments.

Table 3-122 pmevcnt6 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcnt6 RW 0x0 Value of PMU event counter 6

PMU Event Counter 7 register

The pmevcnt7 register is at offset 0x0138. Its characteristics are:

PurposeIndicates the value of PMU event counter 7.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcnt7 register bit assignments.

Figure 3-109 pmevcnt7 register bit assignments
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The following table shows the pmevcnt7 register bit assignments.

Table 3-123 pmevcnt7 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcnt7 RW 0x0 Value of PMU event counter 7

PMU Cycle Counter register

The pmccntr register is at offset 0x0140. Its characteristics are:

PurposeControls the PMU cycle counter.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmccntr register bit assignments.

Figure 3-110 pmccntr register bit assignments
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The following table shows the pmccntr register bit assignments.

Table 3-124 pmccntr register bit assignments

Bits Name Access Reset value Function
[63:40] - RAZ/WI 0x0 Reserved
[39:0] pmccntr RW 0x0 PMU cycle counter

PMU Event Counter Shadow 0 register

The pmevcntsr0 register is at offset 0x0150. Its characteristics are:

PurposeShadow register that indicates the value of PMU event counter 0.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcntsr0 register bit assignments.

Figure 3-111 pmevcntsr0 register bit assignments
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The following table shows the pmevcntsr0 register bit assignments.

Table 3-125 pmevcntsr0 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcntsr0 RW 0x0 Value of PMU event counter 0

PMU Event Counter Shadow 1 register

The pmevcntsr1 register is at offset 0x0158. Its characteristics are:

PurposeShadow register that indicates the value of PMU event counter 1.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcntsr1 register bit assignments.

Figure 3-112 pmevcntsr1 register bit assignments
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The following table shows the pmevcntsr1 register bit assignments.

Table 3-126 pmevcntsr1 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcntsr1 RW 0x0 Value of PMU event counter 1

PMU Event Counter Shadow 2 register

The pmevcntsr2 register is at offset 0x0160. Its characteristics are:

PurposeShadow register that indicates the value of PMU event counter 2.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcntsr2 register bit assignments.

Figure 3-113 pmevcntsr2 register bit assignments
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The following table shows the pmevcntsr2 register bit assignments.

Table 3-127 pmevcntsr2 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcntsr2 RW 0x0 Value of PMU event counter 2

PMU Event Counter Shadow 3 register

The pmevcntsr3 register is at offset 0x0168. Its characteristics are:

PurposeShadow register that indicates the value of PMU event counter 3.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcntsr3 register bit assignments.

Figure 3-114 pmevcntsr3 register bit assignments
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The following table shows the pmevcntsr3 register bit assignments.

Table 3-128 pmevcntsr3 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcntsr3 RW 0x0 Value of PMU event counter 3

PMU Event Counter Shadow 4 register

The pmevcntsr4 register is at offset 0x0170. Its characteristics are:

PurposeShadow register that indicates the value of PMU event counter 4.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcntsr4 register bit assignments.

Figure 3-115 pmevcntsr4 register bit assignments
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The following table shows the pmevcntsr4 register bit assignments.

Table 3-129 pmevcntsr4 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcntsr4 RW 0x0 Value of PMU event counter 4

PMU Event Counter Shadow 5 register

The pmevcntsr5 register is at offset 0x0178. Its characteristics are:

PurposeShadow register that indicates the value of PMU event counter 5.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcntsr5 register bit assignments.

Figure 3-116 pmevcntsr5 register bit assignments
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The following table shows the pmevcntsr5 register bit assignments.

Table 3-130 pmevcntsr5 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcntsr5 RW 0x0 Value of PMU event counter 5

PMU Event Counter Shadow 6 register

The pmevcntsr6 register is at offset 0x0180. Its characteristics are:

PurposeShadow register that indicates the value of PMU event counter 6.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcntsr6 register bit assignments.

Figure 3-117 pmevcntsr6 register bit assignments
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The following table shows the pmevcntsr6 register bit assignments.

Table 3-131 pmevcntsr6 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcntsr6 RW 0x0 Value of PMU event counter 6

PMU Event Counter Shadow 7 register

The pmevcntsr7 register is at offset 0x0188. Its characteristics are:

PurposeShadow register that indicates the value of PMU event counter 7.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmevcntsr7 register bit assignments.

Figure 3-118 pmevcntsr7 register bit assignments
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The following table shows the pmevcntsr7 register bit assignments.

Table 3-132 pmevcntsr7 register bit assignments

Bits Name Access Reset value Function
[63:32] - RAZ/WI 0x0 Reserved
[31:0] pmevcntsr7 RW 0x0 Value of PMU event counter 7

PMU Cycle Counter Shadow register

The pmccntrsr register is at offset 0x0190. Its characteristics are:

PurposeShadow register that controls the PMU cycle counter.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmccntrsr register bit assignments.

Figure 3-119 pmccntrsr register bit assignments
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The following table shows the pmccntrsr register bit assignments.

Table 3-133 pmccntrsr register bit assignments

Bits Name Access Reset value Function
[63:40] - RAZ/WI 0x0 Reserved
[39:0] pmccntrsr RW 0x0 PMU cycle counter

PMU Overflow Status register

The pmovsr register is at offset 0x0198. Its characteristics are:

PurposeIndicates the PMU overflow status.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmovsr register bit assignments.

Figure 3-120 pmovsr register bit assignments
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The following table shows the pmovsr register bit assignments.

Table 3-134 pmovsr register bit assignments

Bits Name Access Reset value Function
[63:9] - RAZ/WI 0x0 Reserved
[8:0] pmovsr RO 0x0

PMU overflow status:

Bit[8]Overflow from cycle counter.
Bits[7:0]Overflow from counters 7-0.

PMU Overflow Status Clear register

The pmovsr_clr register is at offset 0x01A0. Its characteristics are:

PurposeClears the PMU overflow.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmovsr_clr register bit assignments.

Figure 3-121 pmovsr_clr register bit assignments
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The following table shows the pmovsr_clr register bit assignments.

Table 3-135 pmovsr_clr register bit assignments

Bits Name Access Reset value Function
[63:9] - RAZ/WI 0x0 Reserved
[8:0] pmovsr_clr WO 0x0 Write 1 to clear the corresponding bit of the pmovsr register

PMU Control register

The pmcr register is at offset 0x01A8. Its characteristics are:

PurposeControls the PMU and its features.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmcr register bit assignments.

Figure 3-122 pmcr register bit assignments
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The following table shows the pmcr register bit assignments.

Table 3-136 pmcr register bit assignments

Bits Name Access Reset value Function
[63:7] - RAZ/WI 0x0 Reserved
[6] ovfl_intr_en RW 0 Enables assertion of INTREQ on overflow of PMU counters.
[5] cntr_rst RW 0 Enables clearing of live counters on assertion of the pmsr_req bit in the pmsr_req register or PMUSNAPSHOTREQ.
[4:1] cntcfg RW 0x0

Control to group the pair of adjacent 32-bit registers into one 64-bit register.

  • 0 = No pairing.
  • 1 = Pairing of adjacent PMU counters.
  • cntcfg[0] for pmevcnt0/pmevcnt1
  • cntcfg[1] for pmevcnt2/pmevcnt3
  • cntcfg[2] for pmevcnt4/pmevcnt5
  • cntcfg[3] for pmevcnt6/pmevcnt7
[0] pmu_en RW 0 Enables PMU features.

PMU Status register

The pmsr register is at offset 0x01B0. Its characteristics are:

PurposeIndicates the PMU snapshot status.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmsr register bit assignments.

Figure 3-123 pmsr register bit assignments
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The following table shows the pmsr register bit assignments.

Table 3-137 pmsr register bit assignments

Bits Name Access Reset value Function
[63:1] - RAZ/WI 0x0 Reserved
[0] ss_status RO 0 PMU snapshot status

PMU Snapshot Request register

The pmsr_req register is at offset 0x01B8. Its characteristics are:

PurposeRequests a PMU snapshot.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmsr_req register bit assignments.

Figure 3-124 pmsr_req register bit assignments
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The following table shows the pmsr_req register bit assignments.

Table 3-138 pmsr_req register bit assignments

Bits Name Access Reset value Function
[63:1] - RAZ/WI 0x0 Reserved
[0] pmsr_req WO 0 Write 1 to request a PMU snapshot

PMU Snapshot Status Clear register

The pmsr_clr register is at offset 0x01C0. Its characteristics are:

PurposeClears the PMU snapshot status.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the pmsr_clr register bit assignments.

Figure 3-125 pmsr_clr register bit assignments
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The following table shows the pmsr_clr register bit assignments.

Table 3-139 pmsr_clr register bit assignments

Bits Name Access Reset value Function
[63:1] - RAZ/WI 0x0 Reserved
[0] pmsr_clr WO 0 Write 1 to clear the PMU snapshot status

Debug and Trace Identification register

The oly_mn_dt_oly_id register is at offset 0xFF00. Its characteristics are:

PurposeContains the component identification information.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee Table 3-8 Debug event module register summary.

The following figure shows the oly_mn_dt_oly_id register bit assignments.

Figure 3-126 oly_mn_dt_oly_id register bit assignments
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The following table shows the oly_mn_dt_oly_id register bit assignments.

Table 3-140 oly_mn_dt_oly_id register bit assignments

Bits Name Access Reset value Function
[63:15] - RAZ/WI 0x0 Reserved
[14:8] node_id RO 0x0 The node ID of the DT
[7:5] - RAZ/WI 0b000 Reserved
[4:0] oly_id RO 0x2 Indicates that this node is a DT
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