About this book

This book is for the ARM® CoreLink™ CCN-502 Cache Coherent Network.

Product revision status

The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where:

rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.

Intended audience

This book is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the CCN-502.

Using this book

This book is organized into the following chapters:

Chapter 1 Introduction

This chapter describes the CCN-502.

Chapter 2 Functional Description

This chapter describes the functionality of the CCN-502.

Chapter 3 Programmers Model

This chapter describes the programmers model.

Chapter 4 L3 Memory System

This chapter describes the Level 3 memory system.

Chapter 5 Debug

This chapter describes the debug features.

Chapter 6 Performance Optimization and Monitoring

This chapter describes performance optimization techniques for use by system integrators, and the Performance Monitoring Unit (PMU).

Appendix A Signal Descriptions

This appendix describes the external signals of the CCN-502 for a system that includes all possible CCN-502 components.

Appendix B Revisions

This appendix describes the technical changes between released issues of this book.

Glossary

The ARM® Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.

See the ARM® Glossary for more information.

Conventions

Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the ARM® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Timing diagrams

The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Figure 1 Key to timing diagram conventions
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.




Signals

The signal conventions are:

Signal level

The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:

  • HIGH for active-HIGH signals.

  • LOW for active-LOW signals.

Lowercase n

At the start or end of a signal name denotes an active-LOW signal.

Additional reading

This book contains information that is specific to this product. See the following documents for other relevant information.

ARM publications
  • ARM® CoreLink™ CCN-502 Cache Coherent Network Configuration and Sign-off Guide (ARM 100053).
  • ARM® CoreLink™ CCN-502 Cache Coherent Network Integration Manual (ARM 100054).
  • ARM® AMBA® AXI and ACE Protocol Specification (ARM IHI 0022).
  • ARM® AMBA® 5 CHI Architecture Specification (ARM IHI 0050).
  • AMBA® Low Power Interface Specification, ARM® Q-Channel and P-Channel Interfaces (ARM IHI 0068).
  • ARM® Architecture Reference Manual ARMv7-A and ARMv7-R Edition (ARM DDI 0406).
  • ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (ARM DDI 0487).
Other publications
Non-ConfidentialPDF file icon PDF versionARM 100052_0001_00_en
Copyright © 2014, 2015, 2017 ARM Limited or its affiliates. All rights reserved.