3.2 Register summary

The register summary tables list the registers in the CCN-502.

MN register summary

The following table shows the Miscellaneous Node (MN) registers in offset order from the base memory address, PERIPHBASE[43:24]. See 3.1.1 Node configuration register address mapping for information about individual region base addresses.

Table 3-4 MN register summary

Offset Name Type Description
0x0000 secure_access RW Secure Access register
0x0008 errint_status RW Error Interrupt Status register
0x0180 oly_rnf_nodeid_list RO RN-F Node ID register
0x0190 oly_rni_nodeid_list RO RN-I Node ID register
0x01A0 oly_rnidvm_nodeid_list RO RN-D Node ID register
0x01B0 oly_hnf_nodeid_list RO HN-F Node ID register
0x01C0 oly_hni_nodeid_list RO HN-I Node ID register
0x01D0 oly_sn_nodeid_list RO SN Node ID register
0x01E0 oly_comp_list_63_0 RO Component List [63:0] register
0x01E8 oly_comp_list_127_64 RO Component List [127:64] register
0x01F0 oly_comp_list_191_128 RO Component List [191:128] register
0x01F8 oly_comp_list_255_192 RO Component List [255:192] register
0x0200 dvm_domain_ctl RO DVM Domain Control register
0x0210 dvm_domain_ctl_set WO DVM Domain Control Set register
0x0220 dvm_domain_ctl_clr WO DVM Domain Control Clear register
0x0300 err_sig_val_63_0 RO Error Signal Valid [63:0] register
0x0308 err_sig_val_127_64 RO Error Signal Valid [127:64] register
0x0310 err_sig_val_191_128 RO Error Signal Valid [191:128] register
0x0320 err_type_31_0 RO Error Type Value [31:0] register
0x0328 err_type_63_32 RO Error Type Value [63:32] register
0x0330 err_type_95_64 RO Error Type Value [95:64] register
0x0340 err_type_159_128 RO Error Type Value [159:128] register
0x0FD0 periph_id_4_periph_id_5 RO Peripheral ID 4 and Peripheral ID 5 register
0x0FD8 periph_id_6_periph_id_7 RO Peripheral ID 6 and Peripheral ID 7 register
0x0FE0 periph_id_0_periph_id_1 RO Peripheral ID 0 and Peripheral ID 1 register
0x0FE8 periph_id_2_periph_id_3 RO Peripheral ID 2 and Peripheral ID 3 register
0x0FF0 component_id_0_component_id_1 RO Component ID 0 and Component ID 1 register
0x0FF8 component_id_2_component_id_3 RO Component ID 2 and Component ID 3 register
0xFF00 oly_mn_oly_id RO MN Identification register

XP register summary

The following table shows the crosspoint (XP) registers in offset order from the base memory address, PERIPHBASE[43:24]. See 3.1.1 Node configuration register address mapping for information about individual region base addresses.

Table 3-5 XP register summary

Offset Name Type Description
0x0000 xp_routing_control RW XP Routing Control register
0x0008 dev0_nsm_routing_vector RW XP Device 0 Port NSM Routing register
0x0010 dev1_nsm_routing_vector RW XP Device 1 Port NSM Routing register
0x0110 dev0_qos_control RW Device 0 Port QoS Control register
0x0118 dev0_qos_lat_tgt RW Device 0 Port QoS Latency Target register
0x0120 dev0_qos_lat_scale RW Device 0 Port QoS Latency Scale register
0x0128 dev0_qos_lat_range RW Device 0 Port QoS Latency Range register
0x0210 dev1_qos_control RW Device 1 Port QoS Control register
0x0218 dev1_qos_lat_tgt RW Device 1 Port QoS Target Latency register
0x0220 dev1_qos_lat_scale RW Device 1 Port QoS Latency Scale register
0x0228 dev1_qos_lat_range RW Device 1 Port QoS Latency Range register
0x0300 dt_config RW Debug and Trace Configuration register
0x0308 dt_interface_sel RW Debug and Trace Interface Select register
0x0310 dt_cmp_val0_l RW Debug and Trace Comparison Low Value 0 register
0x0318 dt_cmp_val0_h RW Debug and Trace Comparison High Value 0 register
0x0320 dt_cmp_mask0_l RW Debug and Trace Comparison Low Mask 0 register
0x0328 dt_cmp_mask0_h RW Debug and Trace Comparison High Mask 0 register
0x0350 dt_cmp_val1_l RW Debug and Trace Comparison Low Value 1 register
0x0358 dt_cmp_val1_h RW Debug and Trace Comparison High Value 1 register
0x0360 dt_cmp_mask1_l RW Debug and Trace Comparison Low Mask 1 register
0x0368 dt_cmp_mask1_h RW Debug and Trace Comparison High Mask 1 register
0x0370 dt_control RW Debug and Trace Control register, dt_control
0x0378 dt_status RW Debug and Trace Status register
0x0380 dt_status_clr WO Debug and Trace Status Clear register
0x0400 err_syndrome_reg0 RO Error Syndrome 0 register, XP
0x0480 err_syndrome_clr WO XP Error Syndrome Clear register
0x0500 aux_ctl RW Auxiliary Control register, XP
0x0508 byte_par_err_inj WO Byte Parity Error Injection register, XP
0x0600 pmu_event_sel RW PMU Event Select register, XP
0xFF00 oly_xp_oly_id RO XP Identification register

HN-F register summary

The following table shows the Fully-coherent Home Node (HN-F) registers in offset order from the base memory address, PERIPHBASE[43:24]. See 3.1.1 Node configuration register address mapping for information about individual region base addresses.

Table 3-6 HN-F register summary

Offset Name Type Description
0x0000 hnf_cfg_ctrl RW HN-F Configuration Control register
0x0008 hnf_sam_control RW HN-F SAM Control register
0x0010 hn_cfg_pstate_req WO HN-F P-state Request register
0x0018 hn_cfg_pstate_status RO HN-F P-state Status register
0x0020 qos_band RO QoS Band register
0x0028 qos_reservation RW QoS Reservation register
0x0030 rn_starvation RW RN Starvation register
0x0038 hnf_err_inj RW HN-F Error Injection Enable and Setup register
0x0040 hnf_l3_lock_ways RW HN-F L3 Lock Ways register
0x0048 hnf_l3_lock_base0 RW HN-F L3 Lock Base 0 register
0x0050 hnf_l3_lock_base1 RW HN-F L3 Lock Base 1 register
0x0058 hnf_l3_lock_base2 RW HN-F L3 Lock Base 2 register
0x0060 hnf_l3_lock_base3 RW HN-F L3 Lock Base 3 register
0x0068 hnf_byte_par_err_inj WO HN-F Byte Parity Error Injection register
0x0108 hn_cfg_rni_vec RW HN Configuration RN-I Vector register
0x0200 snoop_domain_ctl RO Snoop Domain Control register
0x0210 snoop_domain_ctl_set WO Snoop Domain Control Set register
0x0220 snoop_domain_ctl_clr WO Snoop Domain Control Clear register
0x0300 hn_cfg_l3sf_dbgrd WO HN Debug Read Configuration register
0x0308 l3_cache_access_l3_tag RO L3 Cache Access Tag register
0x0310 l3_cache_access_l3_data RO L3 Cache Access Data register
0x0318 l3_cache_access_sf_tag RO L3 Cache Access SF Tag register
0x0400 err_syndrome_reg0 RO Error Syndrome 0 register, L3 cache
0x0408 err_syndrome_reg1 RO Error Syndrome 1 register, L3 cache
0x0480 err_syndrome_clr WO L3 cache Error Syndrome Clear register
0x0500 hnf_aux_ctl RW HN-F Auxiliary Control register
0x0600 pmu_event_sel RW PMU Event Select register, L3 cache
0xFF00 oly_hnf_misc_oly_id RO HN-F Identification register

HN-I register summary

The following table shows the I/O Home Node (HN-I) registers in offset order from the base memory address, PERIPHBASE[43:24]. See 3.1.1 Node configuration register address mapping for information about individual region base addresses.

Table 3-7 HN-I register summary

Offset Name Type Description
0x0000 pos_control RW PoS Control register
0x0008 pcierc_rni_nodeid_list RW PCIeRC RN-I Node ID List register
0x0400 err_syndrome_reg0 RO Error Syndrome 0 register, HN-I
0x0408 err_syndrome_reg1 RO Error Syndrome 1 register, HN-I
0x0480 err_syndrome_clr WO HN-I Error Syndrome Clear register
0x0500 sa_aux_ctl RW SA Auxiliary Control register, HN-I
0xFF00 oly_hni_oly_id RO HN-I Identification register

Debug event module register summary

The following table shows the debug event module registers in offset order from the base memory address, PERIPHBASE[43:24]. See 3.1.1 Node configuration register address mapping for information about individual region base addresses.

Table 3-8 Debug event module register summary

Offset Name Type Description
0x0000 active_dsm RW Active DSM register
0x0008 trigger_ctl RW Trigger Control register
0x0010 trigger_status RW Trigger Status register
0x0018 trigger_status_clr WO Trigger Status Clear register
0x0020 timer_val RW Timer Value register
0x0028 dt_ctl RW Debug and Trace Control register, dt_ctl
0x0080 dbg_id RW Debug Identification register
0x0100 pmevcnt0 RW PMU Event Counter 0 register
0x0108 pmevcnt1 RW PMU Event Counter 1 register
0x0110 pmevcnt2 RW PMU Event Counter 2 register
0x0118 pmevcnt3 RW PMU Event Counter 3 register
0x0120 pmevcnt4 RW PMU Event Counter 4 register
0x0128 pmevcnt5 RW PMU Event Counter 5 register
0x0130 pmevcnt6 RW PMU Event Counter 6 register
0x0138 pmevcnt7 RW PMU Event Counter 7 register
0x0140 pmccntr RW PMU Cycle Counter register
0x0150 pmevcntsr0 RW PMU Event Counter Shadow 0 register
0x0158 pmevcntsr1 RW PMU Event Counter Shadow 1 register
0x0160 pmevcntsr2 RW PMU Event Counter Shadow 2 register
0x0168 pmevcntsr3 RW PMU Event Counter Shadow 3 register
0x0170 pmevcntsr4 RW PMU Event Counter Shadow 4 register
0x0178 pmevcntsr5 RW PMU Event Counter Shadow 5 register
0x0180 pmevcntsr6 RW PMU Event Counter Shadow 6 register
0x0188 pmevcntsr7 RW PMU Event Counter Shadow 7 register
0x0190 pmccntrsr RW PMU Cycle Counter Shadow register
0x0198 pmovsr RO PMU Overflow Status register
0x01A0 pmovsr_clr RW PMU Overflow Status Clear register
0x01A8 pmcr RW PMU Control register
0x01B0 pmsr RO PMU Status register
0x01B8 pmsr_req WO PMU Snapshot Request register
0x01C0 pmsr_clr WO PMU Snapshot Status Clear register
0xFF00 oly_mn_dt_oly_id RO Debug and Trace Identification register

RN-I register summary

The following table shows the I/O-coherent Requesting Node (RN-I) bridge registers in offset order from the base memory address, PERIPHBASE[43:24]. See 3.1.1 Node configuration register address mapping for information about individual region base addresses.

Table 3-9 RN-I bridge register summary

Offset Name Type Description
0x0008 s0_port_control RW Port S0 Control register, RN-I
0x0010 s0_qos_control RW Port S0 QoS Control register, RN-I
0x0018 s0_qos_lat_tgt RW Port S0 QoS Latency Target register, RN-I
0x0020 s0_qos_lat_scale RW Port S0 QoS Latency Scale register, RN-I
0x0028 s0_qos_lat_range RW Port S0 QoS Latency Range register, RN-I
0x0108 s1_port_control RW Port S1 Control register, RN-I
0x0110 s1_qos_control RW Port S1 QoS Control register, RN-I
0x0118 s1_qos_lat_tgt RW Port S1 QoS Latency Target register, RN-I
0x0120 s1_qos_lat_scale RW Port S1 QoS Latency Scale register, RN-I
0x0128 s1_qos_lat_range RW Port S1 QoS Latency Range register, RN-I
0x0208 s2_port_control RW Port S2 Control register, RN-I
0x0210 s2_qos_control RW Port S2 QoS Control register, RN-I
0x0218 s2_qos_lat_tgt RW Port S2 QoS Latency Target register, RN-I
0x0220 s2_qos_lat_scale RW Port S2 QoS Latency Scale register, RN-I
0x0228 s2_qos_lat_range RW Port S2 QoS Latency Range register, RN-I
0x0500 aux_ctl RW RN-I Auxiliary Control register
0x0600 pmu_event_sel RW PMU Event Select register, RN-I
0xFF00 oly_rni_oly_id RO RN-I Identification register

SBSX register summary

The following table shows the CHI to AXI bridge (SBSX) registers in offset order from the base memory address, PERIPHBASE[43:24]. See 3.1.1 Node configuration register address mapping for information about individual region base addresses.

Table 3-10 SBSX register summary

Offset Name Type Description
0x0500 sa_aux_ctl RW SA Auxiliary Control register, SBSX
0xFF00 oly_sbsx_oly_id RO SBSX Identification register
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