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The DEM contains all the PMU event counting infrastructure. It contains eight 32-bit PMU event counters and a single 40-bit cycle counter.
All PMU events are routed from multiple CCN-502 components over the DTB to the DEM, where all the global performance event counting is performed locally in the DEM.
You can optionally configure each even-aligned register pair, 0/1, 2/3, 4/5, and 6/7, on a pair-by-pair basis to act as a single combined 64-bit counter, with overflows from the least significant register causing counting in the most significant register.
There are eight DTB bits and eight PMU counters. This provides a one-to-one correspondence between the DTB bit and the PMU counter, and requires no additional multiplexing between the DTB and the PMU counters. However, for register pairs, the least significant register counts events on its normal corresponding DTB input, but the most significant register ignores its corresponding DTB input and instead counts overflows from the least significant register.
You can snapshot the PMU registers for greater accuracy in counter and event collection from an outside source. When a snapshot request is made, the CCN-502 copies all live counters into shadow copies, that software or hardware can read without interrupting the live counting functionality.
The DEM includes hardware and software control of the snapshot request activity:
For both snapshot request control mechanisms, the DEM enables optional clearing of the live counters after they are copied to the shadow copies. This simplifies the snapshotting and counting process in a snapshot system.
Because the PMU counters count events sent over the DTB, you can use the PMU counters to count debug events, such as functional watchpoint matches, instead of traditional performance events.
The DEM detects overflow of any of the nine PMU counters, and logs an overflow indicator in the pmovsr register. In addition, the DEM can optionally cause the CCN-502 interrupt, INTREQ, to be asserted on PMU overflow, to enable software to handle the overflow condition.