2.1 About the functions

This section describes the functional blocks in the CCN-502.

The CCN-502 combines interconnect and coherency functions into a single module. It supports connectivity for up to 4 CHI masters, one AXI4/ACE-Lite slave, up to 9 AXI4/ACE-Lite/ACE-Lite+DVM masters, plus optional Distributed Virtual Memory (DVM) message support on these interfaces to manage distributed Memory Management Units (MMUs).

The following figure shows a block-level view of an example configuration of the CCN-502.

Figure 2-1 CCN-502 block diagram
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A complete SoC system includes many devices. This section only describes the devices that are deliverables in the CCN-502 product.

This section contains the following subsections:
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