2.14.3 Power states

This section lists the valid CCN-502 power states and shows the power state transition diagram.

The following table shows the valid CCN-502 power states and their requirements.

Table 2-8 CCN-502 power states

State Description Control logic Snoop filter power state L3 way[7:0] power state L3 way[15:8] power state
FAM Full run mode On On On On
HAM Run mode with L3H1 (L3 upper ways) disabled. On On On Off
SF Run mode with L3H1 and L3H2 disabled. On On Off Off
NOL3 Run mode with L3H1, L3H2, and SF disabled. On Off Off Off
FAM Dyn. Ret. Run mode with L3H1, L3H2, and SF in retention. On Retention Retention Retention
HAM Dyn. Ret. Run mode with L3H1 and SF in retention, and L3H2 in powerdown. On Retention Retention Off
SF Dyn. Ret. Run mode with SF in retention, and L3H1 and L3H2 in powerdown. On Retention Off Off
FAM Static Ret. Shutdown mode with L3H1, L3H2, and SF in retention. Off Retention Retention Retention
HAM Static Ret. Shutdown mode with L3H1 and SF in retention, and L3H2 in powerdown. Off Retention Retention Off
SF Static Ret. Shutdown mode with SF in retention, and L3H1 and L3H2 in powerdown. Off Retention Off Off
OFF Shutdown. Off Off Off Off

The L3 cache operates in four main operational modes:

FAMFull-Associativity Mode, where the snoop filter and the entire L3 cache are used.
HAMHalf-Associativity Mode, where the snoop filter is enabled but the upper half of the L3 ways are disabled and powered off.
SFONLYSnoop-Filter-Only mode, where the snoop filter is enabled but all the L3 cache is powered off.
NOL3No-L3 mode, where the snoop filter and L3 cache are disabled and powered off.

The following figure shows the valid power states and transitions for a CCN-502 system.

Figure 2-15 Power state transitions
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From FAM, HAM, or SFONLY, the L3 cache can enter a dynamic retention mode, where:

  • The logic power is on.
  • The voltage to the RAMs is on, but is reduced to a level that is sufficient for bitcell retention but insufficient for normal operation.

From these states, the L3 cache can also enter a static retention mode, where:

  • The logic power is turned off.
  • The voltage to the RAMs is on, but is reduced to a level that is sufficient for bitcell retention but insufficient for normal operation.

The difference between the dynamic and static retention modes is that dynamic retention is entered because of a dynamic activity or inactivity indicator from the HN-F to the SoC. This is an output of the HN-F that is used to determine periods of inactivity long enough to warrant entering retention mode, but not long enough or not the type of inactivity to make the SoC place the L3 and SF in static retention. In addition to the static retention modes, the control logic can be powered down from the NOL3 state, at which point the CCN-502 is fully off.

All activity that is required to enable safe transition between the respective power states is performed automatically by the HN-Fs in response to input P-Channel P-state transitions. No additional activity is required of the SoC logic to enable transitions between power states. For example, the HN-F performs clean and invalidation of half of the ways of the L3 and clean and invalidation of all ways of the L3, as required by the respective power state transitions.

Note:

The power controller cannot make any power transitions while the control logic is powered off. For example, if the power controller wants to transition from FAM static retention to OFF, it must transition through the FAM and NOL3 power states. This is because the RAMs must be flushed before they are powered down.
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