A.4 Power management signals

The following tables show the power management signals.

The following table shows the power management signals for the logic power domain.

Table A-7 Power management signals for logic power domain

Signal Type Description Connection information
PREQ_LOGIC Input Indicates a request for a power state transition. Connect to external power management controller or tie LOW if unused.
PSTATE_LOGIC[0] Input

The power state to which a transition is requested.a

The following table shows the values for this signal.

Connect to external power management controller or tie HIGH if unused.
PACCEPT_LOGIC Output Indicates acknowledgment of the power state transition and completion of the power state transition within the CCN-502. Connect to external power management controller.
PDENY_LOGIC Output Indicates denial of the power state transition.
PACTIVE_LOGIC Output Hint that indicates activity across the CCN-502. When LOW, it hints at the possibility of entering static retention or the OFF state.

The following table shows the PSTATE_LOGIC[0] values.

Table A-8 PSTATE_LOGIC[0] values

Value State Definition
0 OFF Prepare to power down, that is, close all CHI links.
1 ON Enable activation of CHI links.

The following table shows the power management signals for the optional CCN502_RNF_DSSB and CCN502_SNF_DSSB power domains.

Table A-9 Power management signals for optional CCN502_RNF_DSSB and CCN502_SNF_DSSB power domains

Signal Type Description Connection information
PREQ_DEV Input Indicates a request for a power state transition. Connect to external power management controller or tie LOW if unused.
PSTATE_DEV[0] Input

The power state to which a transition is requested.a

The following table shows the values for this signal.

Connect to external power management controller or tie HIGH if unused.
PACCEPT_DEV Output Indicates acknowledgment of the power state transition and completion of the power state transition within the CCN-502. Connect to external power management controller.
PDENY_DEV Output Indicates denial of the power state transition.
PACTIVE_DEV Output Hint that indicates activity across the CCN-502. When LOW, it hints at the possibility of entering static retention or the OFF state.

The following table shows the PSTATE_DEV[0] values.

Table A-10 PSTATE_DEV[0] values

Value State Definition
0 OFF Prepare to power down, that is, close all CHI links.
1 ON Enable activation of CHI links.

The following table shows the power management signals for the snoop filter RAM power domain.

Table A-11 Power management signals for snoop filter RAM power domain

Signal Type Description Connection information
PREQ_SF Input Indicates a request for a power state transition. Connect to external power management controller or tie LOW if unused.
PSTATE_SF[1:0] Input

The power state to which a transition is requested.a

The following table shows the values for this signal.

Connect to external power management controller or tie to 0b11 if unused.
PACCEPT_SF Output Indicates acknowledgment of the power state transition and completion of the power state transition within the CCN-502. Connect to external power management controller.
PDENY_SF Output Indicates denial of the power state transition.
PACTIVE_SF Output Hint that indicates activity in the snoop filter. When LOW, it hints at the possibility of entering dynamic retention. When HIGH, it is an indication that the snoop filter is required and that the SoC must exit dynamic retention.

The following table shows the PSTATE_SF[1:0] values.

Table A-12 PSTATE_SF[1:0] values

Value State Definition
0b00 OFF Prepare to power down. Activity depends on previous P-state.
0b01 MEM_RET HN-F prohibits access to snoop filter RAM arrays.
0b10 DYN_RET HN-F prohibits access to snoop filter RAM arrays.
0b11 ON Normal usage of snoop filter. Additional activity depends on previous P-state.

The following table shows the power management signals for the L3 tag/data RAMs in way[7:0].

Table A-13 Power management signals for L3 tag/data RAMs way[7:0]

Signal Type Description Connection information
PREQ_L3RAM0 Input Indicates a request for a power state transition. Connect to external power management controller or tie LOW if unused.
PSTATE_L3RAM0[1:0] Input

The power state to which a transition is requested.a

The following table shows the values for this signal.

Connect to external power management controller or tie to 0b11 if unused.
PACCEPT_L3RAM0 Output Indicates acknowledgment of the power state transition and completion of the power state transition within the CCN-502. Connect to external power management controller.
PDENY_L3RAM0 Output Indicates denial of the power state transition.
PACTIVE_L3RAM0 Output Hint that indicates activity in way[7:0] of the L3 RAMs. When LOW, it hints at the possibility of entering dynamic retention. When HIGH, it is an indication that these L3 RAMs are required and that the SoC must exit dynamic retention.

The following table shows the PSTATE_L3RAM0[1:0] values.

Table A-14 PSTATE_L3RAM0[1:0] values

Value State Definition
0b00 OFF Prepare to power down. Activity depends on previous P-state.
0b01 MEM_RET HN-F prohibits access to L3 RAM arrays for way[7:0].
0b10 DYN_RET HN-F prohibits access to L3 RAM arrays for way[7:0].
0b11 ON Normal usage of L3 RAM arrays for way[7:0]. Additional activity depends on previous P-state.

The following table shows the power management signals for the L3 tag/data RAMs in way[15:8].

Table A-15 Power management signals for L3 tag/data RAMs way[15:8]

Signal Type Description Connection information
PREQ_L3RAM1 Input Indicates a request for a power state transition. Connect to external power management controller or tie LOW if unused.
PSTATE_L3RAM1[1:0] Input

The power state to which a transition is requested.a

The following table shows the values for this signal.

Connect to external power management controller or tie to 0b11 if unused.
PACCEPT_L3RAM1 Output Indicates acknowledgment of the power state transition and completion of the power state transition within the CCN-502. Connect to external power management controller.
PDENY_L3RAM1 Output Indicates denial of the power state transition.
PACTIVE_L3RAM1 Output Hint that indicates activity in way[15:8] of the L3 RAMs. When LOW, it hints at the possibility of entering dynamic retention. When HIGH, it is an indication that these L3 RAMs are required and that the SoC must exit dynamic retention.

The following table shows the PSTATE_L3RAM1[1:0] values.

Table A-16 PSTATE_L3RAM1[1:0] values

Value State Definition
0b00 OFF Prepare to power down. Activity depends on previous P-state.
0b01 MEM_RET HN-F prohibits access to L3 RAM arrays for way[15:8].
0b10 DYN_RET HN-F prohibits access to L3 RAM arrays for way[15:8].
0b11 ON Normal usage of L3 RAM arrays for way[15:8]. Additional activity depends on previous P-state.
a If MultiCycle Path (MCP), the MCP duration must be ≤8 cycles to the last flop to receive this signal. This is a requirement for implementation.
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