2.14.5 L3 data RAM retention control

This section describes how to use the l3_reten_hx signal when the RAM is in retention mode.

The HN-F L3 data RAM quadwords have an input, l3_reten_hx, that can be used for dynamic retention control. This signal asserts four cycles before the data RAMs are accessed, either read or write, and is held for the duration of the access, accounting for RAM latency. This enables the RAMs to be put in a retention mode, provided the 4-cycle wakeup is sufficient to exit retention mode and allow a read or write.

The following figure shows the l3_reten_hx signal behavior for a single L3 data RAM read. It asserts four cycles before the RAM read enable, and is held for the duration of the RAM read, three cycles after the RAM read enable in this case, showing the behavior of 3-cycle data RAMs.

Figure 2-19 l3_reten_hx timing for single L3 data RAM read
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