A.2 Clock and reset signals

The CCN-502 includes 1-7 clock inputs, depending on the configuration of an instantiation. It also includes three types of clock-enable input pins for frequency-divided operation of AMBA and debug and trace interfaces.

The CCN-502 Input/Output (I/O) signals are both synchronous and asynchronous to the clocks. Any specific requirements of the I/O, including asynchronous requirements and specific physical implementation requirements such as multicycle path constraints, are included in the I/O description.

The following table shows the CCN-502 clock and reset signals.

Table A-1 CCN-502 clock and reset signals

Signal Type Description Connection information
GCLK0 Input Clock input for Domain0, whose definition is configuration-dependent. See Figure 2-9 CCN-502 clock domain, fully synchronous. Connect to global clock for CCN-502
nSRESET Input CCN-502 reset, active-LOW. Connect to global reset for CCN-502

Clocks and resets for the optional RN-F DSSBs

The following table shows the CCN-502 clock and reset signals with the optional CCN502_RNF_DSSB.

Table A-2 CCN-502 clock and reset signals with optional CCN502_RNF_DSSB

Signal Type Description Connection information
GCLK0 Input Clock input for Domain0, whose definition is configuration-dependent. See Figure 2-9 CCN-502 clock domain, fully synchronous. Connect to global clock for CCN-502

RXREQGCLKCD_NID<x>

Where <x> is 1, 5, 7, or 11 (6XP/2HNF) or <x> is 1, 7, 9, or 15 (8XP/4HNF).

Clock input for REQ flit receive FIFO of the XP DSSB attached to Node ID <x>a. Connect to input clock from Node ID <x> CCN502_RNF_DSSB

RXRSPGCLKCD_NID<x>

Where <x> is 1, 5, 7, or 11 (6XP/2HNF) or <x> is 1, 7, 9, or 15 (8XP/4HNF).

Clock input for RSP flit receive FIFO of the XP DSSB attached to Node ID <x>a.

RXDATGCLKCD_NID<x>

Where <x> is 1, 5, 7, or 11 (6XP/2HNF) or <x> is 1, 7, 9, or 15 (8XP/4HNF).

Clock input for DAT flit receive FIFO of the XP DSSB attached to Node ID <x>a.

TXRSPGCLK_NID<x>

Where <x> is 1, 5, 7, or 11 (6XP/2HNF) or <x> is 1, 7, 9, or 15 (8XP/4HNF).

Output Clock output for RSP flit receive FIFO in CCN502_RNF_DSSB of Node ID <x>a. Connect output to Node ID <x> CCN502_RNF_DSSB

TXDATGCLK_NID<x>

Where <x> is 1, 5, 7, or 11 (6XP/2HNF) or <x> is 1, 7, 9, or 15 (8XP/4HNF).

Clock output for DAT flit receive FIFO in CCN502_RNF_DSSB of Node ID <x>a.

TXSNPGCLK_NID<x>

Where <x> is 1, 5, 7, or 11 (6XP/2HNF) or <x> is 1, 7, 9, or 15 (8XP/4HNF).

Clock output for SNP flit receive FIFO in CCN502_RNF_DSSB of Node ID <x>a.
nSRESET Input CCN-502 reset, active-LOW. Connect to global reset for CCN-502

The following table shows the clock and reset signals for the optional CCN502_RNF_DSSB.

Table A-3 Clock and reset signals for optional CCN502_RNF_DSSB

Signal Type Description Connection information
GCLKCD Input Clock input for device domain. Connect device domain clock to CCN502_RNF_DSSB input
GCLKCD_RXREQ Clock input for device domain, used to generate TXREQGCLKCD_CCN output.
GCLKCD_RXRSP Clock input for device domain, used to generate TXRSPGCLKCD_CCN output.
GCLKCD_RXDAT Clock input for device domain, used to generate TXDATGCLKCD_CCN output.
RXRSPGCLK_CCN Clock input for RSP flit receive FIFO in CCN502_RNF_DSSB. Connect input to TXRSPGCLK_NID<x> output of the CCN-502
RXDATGCLK_CCN Clock input for DAT flit receive FIFO in CCN502_RNF_DSSB. Connect input to TXDATGCLK_NID<x> output of the CCN-502
RXSNPGCLK_CCN Clock input for SNP flit receive FIFO in CCN502_RNF_DSSB. Connect input to TXSNPGCLK_NID<x> output of the CCN-502
TXREQGCLKCD_CCN Output Clock output for REQ flit receive FIFO of XP DSSB attached to the CCN502_RNF_DSSB. Connect output to RXREQGCLKCD_NID<x> input of the CCN-502
TXRSPGCLKCD_CCN Clock output for RSP flit receive FIFO of XP DSSB attached to the CCN502_RNF_DSSB. Connect output to RXRSPGCLKCD_NID<x> input of the CCN-502
TXDATGCLKCD_CCN Clock output for DAT flit receive FIFO of XP DSSB attached to the CCN502_RNF_DSSB. Connect output to RXDATGCLKCD_NID<x> input of the CCN-502
nDEVRESET Input Processor domain reset for CCN502_RNF_DSSB, active-LOW. Connect to global reset for processor connected to CCN502_RNF_DSSB

 

Clocks and resets for the optional SN-F DSSBs

The following table shows the CCN-502 clock and reset signals with the optional CCN502_SNF_DSSB.

Table A-4 CCN-502 clock and reset signals with optional CCN502_SNF_DSSB

Signal Type Description Connection information
GCLK0 Input Clock input for Domain0, whose definition is configuration-dependent. See Figure 2-9 CCN-502 clock domain, fully synchronous. Connect to global clock for CCN-502

RXRSPGCLKCD_NID<x>

Where <x> is 2 or 8 (6XP/2HNF) or <x> is 2, 4, 10, or 12 (8XP/4HNF).

Input Clock input for RSP flit receive FIFO of the XP DSSB attached to Node ID <x>a. Connect to input clock from Node ID <x> CCN502_SNF_DSSB

RXDATGCLKCD_NID<x>

Where <x> is 2 or 8 (6XP/2HNF) or <x> is 2, 4, 10, or 12 (8XP/4HNF).

Clock input for DAT flit receive FIFO of the XP DSSB attached to Node ID <x>a.

TXREQGCLK_NID<x>

Where <x> is 2 or 8 (6XP/2HNF) or <x> is 2, 4, 10, or 12 (8XP/4HNF).

Output Clock output for REQ flit receive FIFO in CCN502_SNF_DSSB of Node ID <x>a. Connect output to Node ID <x> CCN502_SNF_DSSB

TXDATGCLK_NID<x>

Where <x> is 2 or 8 (6XP/2HNF) or <x> is 2, 4, 10, or 12 (8XP/4HNF).

Clock output for DAT flit receive FIFO in CCN502_SNF_DSSB of Node ID <x>a.
nSRESET Input CCN-502 reset, active-LOW. Connect to global reset for CCN-502

The following table shows the clock and reset signals for the optional CCN502_SNF_DSSB.

Table A-5 Clock and reset signals for optional CCN502_SNF_DSSB

Signal Type Description Connection information
GCLKCD Input Clock input for device domain Connect device domain clock to CCN502_SNF_DSSB input
GCLKCD_RXRSP Clock input for device domain, used to generate TXRSPGCLKCD_CCN output
GCLKCD_RXDAT Clock input for device domain, used to generate TXDATGCLKCD_CCN output
RXREQGCLK_CCN Clock input for REQ flit receive FIFO in CCN502_SNF_DSSB Connect input to TXREQGCLK_NID<x> output of the CCN-502
RXDATGCLK_CCN Clock input for DAT flit receive FIFO in CCN502_SNF_DSSB Connect input to TXDATGCLK_NID<x> output of the CCN-502
TXRSPGCLKCD_CCN Output Clock output for RSP flit receive FIFO of XP DSSB attached to the CCN502_SNF_DSSB Connect output to RXRSPGCLKCD_NID<x> input of the CCN-502
TXDATGCLKCD_CCN Clock output for DAT flit receive FIFO of XP DSSB attached to the CCN502_SNF_DSSB Connect output to RXDATGCLKCD_NID<x> input of the CCN-502
nDEVRESET Input DMC domain reset for CCN502_SNF_DSSB, active-LOW Connect to global reset for DMC connected to CCN502_SNF_DSSB
a See Figure 2-10 CCN-502 clock domains with optional DSSBs.
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