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This section describes CCN-502 addressing capabilities.
The CCN-502 includes a 44-bit physical address capability on several interfaces. However, this capability exists primarily to enable DVM messages compliant with ARMv8-A TLB maintenance operations and to support potential address-space expansion in other members of the Cache Coherent Network product line. An SoC designer using the CCN-502 is not expected to make use of more than 40 bits of the physical address space.