2.8.2 System requirements

This section describes system requirements.

The system requirements are as follows:

  • All non-PCIe I/O slave devices must complete all writes without creating any dependency on a transaction in the PCIe subsystem.
  • All non-PCIe I/O masters connected to the same RN-I as a PCIe master must not send any transactions that target or apply to I/O slave devices downstream of the HN-I.
  • If an SMMU is placed in the path between the PCIe master interface and the RN-I slave interface, table-walk requests from the SMMU can only be sent to memory through the HN-F.
  • ARM recommends that you set the wuo bit in the RN-I Auxiliary Control register of the RN-I that connects to the PCIe master. The wuo bit enables high bandwidth strongly-ordered coherent writes, that is, PCIe ordered coherent writes. If there are multiple RN-Is with PCIe masters attached, you can set this bit for only one of those RN-Is.
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