|Non-Confidential||PDF version||ARM 100052_0001_00_en|
|Home > Functional Description > Clocking and resets > Reset|
The CCN-502 has a single global reset input signal, nSRESET. If the network includes the optional DMC or DSSBs, then each CCN502_RNF_DSSB or CCN502_SNF_DSSB also has an nDEVRESET reset input.
nSRESET is an active-LOW signal, and is used as an input for each CCN-502 component. All CCN-502 components locally synchronize their nSRESET input, so that nSRESET at the component boundary can be asynchronously or synchronously asserted and deasserted.
There are no specific requirements for the relative timing of nSRESET assertion or deassertion as received by the respective components in a CCN-502 system. That is, all versions of nSRESET in a CCN-502 can assert or deassert asynchronously and at different times as required by the implementation of what is expected to be a multicycle path to each component. However, all components must see at least 24 concurrent cycles of an asserted nSRESET before nSRESET is deasserted. This 24-cycle time period is measured from the time nSRESET is asserted at the boundary of the last CCN-502 component to receive nSRESET and is measured using the period of the slowest global clock input.
All CCN-502 clock inputs must be active during the required 24-cycle period of nSRESET assertion, and must remain active for at least 10 cycles following deassertion of nSRESET.
When the optional DMC or processor DSSBs are included, the CCN502_RNF_DSSB and CCN502_SNF_DSSB blocks have a reset input signal, nDEVRESET. This signal is active-LOW, and must connect to the primary reset input of the device.
For a protocol device to communicate with other protocol devices after reset, that device:
This means that: