4.1 About the L3 memory system
The L3 memory system consists of the HN-F protocol node in the CCN-502.
There are 2 (6XP/2HNF) or 4 (8XP/4HNF)
instances of the HN-F, and each HN-F node or slice has the following features:
- 0KB, 128KB, 512KB, 1MB, or 2MB of L3 cache data
RAM and tag RAM.
- Combined Point-of-Coherency (PoC) and
- 512KB, 2MB, or 4MB snoop filter
Each HN-F in the CCN-502 is configured to manage a specific portion of the total address
space. For each portion of the address, each HN-F:
- Can cache data in L3.
- Manages PoC and PoS functionality for ordering and coherency.
- Tracks RN-F caching in the snoop filter.
The L3 memory system has the following features:
- Physically Indexed and Physically
- Coherency granule is a fixed length of 64 bytes. L3 cache line size
is a fixed length of 64 bytes.
- Both L3 and snoop filter are 16-way set-associative.
- The L3 and snoop filter victim selection policy is:
- Find first invalid way.
- Pseudo random if all ways are valid.
- L3 and snoop filter arrays:
- Supports two or three cycle non-pipelined tag and data
- L3 tag, snoop filter tag, and L3 data arrays are single
ported, supporting one read or write access with no concurrency
- L3 tag, snoop filter tag, and L3 data arrays are ECC
(SECDED) protected, with inline ECC checking and correction. SECDED means
Single-Error Correction and Double-Error
- 32 entry address and data buffer, known as PoC
Queue (POCQ),which the 4HNF can have 16 entry POCQ to service:
- All transactions from the CHI interface.
- L3 modified evictions to the memory controller.
- Snoop filter evictions.
- Supports QoS-based protocol flow control:
- PoC and PoS resources (POCQ) are allocated or rejected for
protocol retry, based on the QoS class.
- POCQ resources are watermarked for different QoS classes
with user-configurable options.
- Starvation prevention for lower-priority QoS classes.
- QoS-based static grantee selection for CHI architecture credit
- QoS priority-based request selection to the memory controller.
- Supports allocation in the L3 cache from snoop intervention. This
enables data sharing through the L3 for multiple sharers.
- L3 state includes caching RN-F
IDentifier (RNFID) to detect dynamic read sharing.
- 44-bit physical address support.
- PoC and PoS for all Snoopable and Non-snoopable, and Cacheable and Non-cacheable address space.
- Supports ECC scrubbing for single bit ECC errors.
- Software-controlled error injection support to enable testing of
software error handler routine.
- Power-management states to support:
- Full powerdown of the L3 and snoop filter. HN-F only mode
when both L3 and snoop filter are powered down.
- Half the L3 ways powered down.
- Retention for L3 and snoop filter.
- L3 full powerdown with snoop filter on, when in snoop filter
- ARM TrustZone® technology support in L3 and snoop filter.